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Datasheet File OCR Text:

Mobile Platform Controller plus 8 Mbit LPC Firmware Flash
SST79LF008
SST79LF008 Notebook System Controller with 8 Mbit LPC Firmware Flash
Advance Information
FEATURES:
* 8 Mbit LPC Firmware Memory SuperFlash device with integrated LPC Keyboard, System configuration, and Power Management controller * ACPI 2.0 Compliant * Conforms to LPC Interface Specification v1.1 - Includes support for Multi-byte Firmware Memory Read/Write Cycles - Firmware Memory 1-, 2-, 4-, 16-, and 128-byte Read Cycles - Firmware Memory 1-, 2-, and 4-byte Write Cycles - 15.7 MB/sec data transfer rate @ 33MHz clock for Multi-Byte Read - One ID pin for LPC Firmware Memory Device selection * LPC Firmware Memory - 8 Mbit Single Block of on-chip SuperFlash memory with two Shared-ROM modes - Mode 1: 7 Mbit (896 KByte) for system BIOS and 1 Mbit (128 KByte) for 8051 firmware - Mode 2: 7.5 Mbit (960 KByte) for system BIOS and 0.5 Mbit (64 KByte) for 8051 firmware - Uniform 4 KByte Sectors and 64 KByte Blocks with Erase capability - 19 Lockable Blocks: one 16 KByte Boot Block, two 8 KByte Parameter Blocks, one 32 KByte Parameter Block, fifteen 64 KByte Main Blocks - Block Locking Registers for individual block Read-Lock, Write-Lock, and Lock Down protection - Lockable bottom 4 KByte sector for 8051 boot firmware - Erase-Suspend allowing Read or Program of the other blocks - Two-Cycle Command Set * Non-Volatile Registers (NVR) - 64-bit SST Pre-Programmed Identifier - 192-bit OTP User Unique Identifier with WriteLock protection - 3 KByte OTP User NVR area (UNVR) - 4 KByte Erasable NVR area (ENVR) with Write-/ Read-Lock protection * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Fast Erase/Program Operations - Sector-Erase Time: 55 ms (typical) - Block-Erase Time: 55 ms (typical) - Word-Program Time: 15 s (typical) * aLPC mode for Rapid Factory Programming - Alternate LPC bus (aLPC) for in-system and factory programming - Auto Address Increment (AAI) - Multi-Byte Program - Chip Rewrite Time: 12 seconds (typical) Embedded Enhanced 8051 MCU - 3- or 6-clock (selectable) per-instruction cycle - Up to 33 MHz 8051 operating frequency - Up to 128 KByte Program Address Space - 256 Byte standard 8051 RAM - 2 KByte on-chip expanded Data RAM / Executable RAM (Scratch ROM) - Extended up to 2 KByte Stack Space - Four Levels of Interrupt Priorities and Twelve Interrupt Vectors - Power-saving IDLE and Power-Down modes - Multiple Maskable Hardware Wake-up Events (sources include: Hibernation timer, LPC, serial interfaces, all GPIOs, and others) LPC Host Interfaces - One 8042-style legacy KBC interface channel - Two ACPI EC interface channels - 32 8-bit LPC Host-to-8051 Mailbox Registers - Programmable Base addresses for all channels System Interrupts - IRQ1 and IRQ12 via serialized IRQ Interface - Two EC SCI event outputs - SMI via Serialized IRQ2 or SMI event output Hardware GA20 and CPU Reset Outputs Control 16 x 8 (24 pins) Key Scan Matrix expandable to 16 x 14 (30 pins) Three Independent PS/2 Ports - Hardware driven receive and transmit protocols - Integrated time-out control Two SMBus controllers/Three SMBus channels - SMBus 2.0 compliant - Master and Slave operation - Internal multiplexer for SMBus channel selection Full-Duplex Enhanced UART channel SPI Master/Slave channel
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(c)2006 Silicon Storage Technology, Inc. S71320-01-000 10/06 1
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information * Eight-channel ADC with 10-bit resolution * Four-channel DAC with 8-bit resolution * Two 8-bit Fan Tachometer channels with clock prescaler * Three PWM channels with 8-bit resolution and independent prescaler * Five direct LED control channels with blinking capability * Watchdog Timer * Hibernation Timer * Three 16-bit Timers/Counters * Configurable 5-Volt Tolerant General Purpose I/O Ports (GPIO) - 112 GPIOs with 35 dedicated (non-multiplexed with alternative function) - Any dedicated GPIO or GPIO with disabled alternative function can be configured as Edge-Trigger maskable Interrupt and/or Wake Up event * Clocks - Standard 32.768 KHz crystal oscillator - 10 to 20MHz fail-safe internal ring oscillator (automatic switch-on if Power-Good signal is deasserted) - Up to 33MHz core clock derived directly from the external clock input or via internal PLL * Single 3.0-3.6V operation with 5V tolerant I/O (except LPC bus and analog I/O) * Low Power Consumption - Idle Mode supply current: 17mA (typical) - Power-Down mode supply current: 100 A (typical) * Temperature Range: 0C to 70C * Packages Available - 176-lead LQFP - 176-ball TFBGA * All non-Pb (lead-free) devices are RoHS Compliant
PRODUCT DESCRIPTION
The SST79LF008 is a high-performance LPC flash device with integrated PC Keyboard/Auxiliary device controller (KBC) and ACPI embedded controller (EC). This product is well suited for a wide range of mobile internet computing applications which require high integration (small form factor), superior power, and thermal management capability. SST79LF008 includes 8Mbit of SuperFlash memory, which can be used to store system BIOS as well as KBC/EC firmware. Either 128 KByte (1 Mbit) or 64 KByte (0.5 Mbit) of the SuperFlash memory can be allocated for the KBC/EC code providing, respectively, 896 KByte (7.0 Mbit) or 960 KByte (7.5 Mbit) for the system BIOS memory. The SST79LF008 features in-system programming, which provides maximum flexibility in the manufacturing environment as well as a mechanism for updating the keyboard firmware code, the main system BIOS code, and adding new functionality in the end-user environment in order to meet the latest market demands. It also speeds up software development and improves the overall time-to-market. The SST79LF008 is manufactured with SST's proprietary, high-performance SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturing capability compared with alternate approaches. The device significantly improves performance and reliability, while lowering the power consumption. The SST79LF008 is designed to be compatible with any LPC bus compatible host controllers, such as the ICHx or other south-bridge devices of PC chipsets for PC-BIOS application. It provides several mechanisms controlled by KBC/EC firmware and/or LPC host for code and data storage protection. SST79LF008 also includes an additional 4 Kbyte of lockable, open-after-reset SuperFlash memory, which can be used as secure ENVR storage. SST79LF008 on-chip peripherals, including PS/2 ports, Matrix scanner, SMBus controllers, and ADC/DAC/PWM with flexible GPIO configuration, provide necessary hardware support for the KBC/EC functions on the mobile PC platforms.
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
2
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
TABLE OF CONTENTS
1.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 I/O Type Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.0 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3 Data Memory Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4 Special Function Registers (SFRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.1 SFR Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.2 SFR References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5 Memory Mapped Configuration Registers (MMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.5.1 MMCR References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.5.2 JEDEC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.0 FLASH MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.1 SuperFlash Memory Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.1 ENVR / UNVR Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.2 Programming Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3 Shared ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.4 In-Application Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Scratch ROM Mapping Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IAP Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Selection for IAP Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IAP Mode Commands Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4.1 No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4.2 Sector-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4.3 Block-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4.4 Word-Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4.5 Erase-Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4.6 Erase-Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4.7 Word-Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.5 SuperFlash Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 4.4.2 4.4.3 4.4.4 46 47 47 48 48 48 48 49 49 49 49 50
4.5 BootRom Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6 LPC Flash Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.7 8051 Controlled Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.8 aLPC MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.8.1 4.8.2 4.8.3 4.8.4 Alternate LPC (aLPC) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aLPC Access to BIOS and KBC Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aLPC Memory Write Operation with Auto-Address Increment and Multi-Byte Programming . . . aLPC Memory Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S71320-01-000
55 57 57 60
10/06
(c)2006 Silicon Storage Technology, Inc.
3
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 4.8.5 aLPC I/O Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.8.6 aLPC Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.0 POWER, RESET AND CLOCK SOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.1 Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.2 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Brown-out Detection Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer (WDT) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aLPC Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LPC Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8051 Firmware Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LPC Interface Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 69 69 69 69 70 70 70 70 71 71 72 74 75 76
5.3 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3.1 Clock Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1.1 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Clock Selection Control and Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Clock Switching after Power On and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3.1 Power Good Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 Clock Switching in Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.0 8051 EMBEDDED MICROCONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1 8051 MCU Enhancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2 8051 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2.1 16-Bit Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2.2 17-Bit Contiguous Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2.2.1 8051 Instruction Set Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3 8051 Machine Cycle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4 8051 Dual Data Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.5 8051 Stack Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.0 LPC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.1 LPC Bus Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.2 LPC Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.2.1 Firmware Memory Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.2.2 LPC Memory Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.2.3 LPC I/O Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3 LPC Flash Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 Read Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Device Identifier Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sector Erase Command and Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Erase Suspend Command and Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 7.3.8 User Unique ID Read, Program and Lockout Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.3.9 Enter UNVR (3K OTP) / Enter ENVR Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.3.10 Force / Release LPC Soft Reset Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4 LPC Abort Mechanism and Invalid Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.1 Response to Invalid Fields for Firmware Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.2 Response to Invalid Fields for LPC Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.5 Multiple Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.5.1 Multiple Device Selection for Firmware Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.5.2 Multiple Device Selection for LPC Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.6 LPC Memory Mapped Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.6.1 7.6.2 7.6.3 7.6.4 Flash Memory Block Locking Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JEDEC ID Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-byte Read/Write Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unique ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 95 95 96
7.7 PCI CLOCK RUN CONTROL SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.8 LPC Power Down Protocol Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.0 INTERRUPTS AND WAKEUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.1 SST79LF008 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.2 SST79LF008 Wakeups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.3 INTERRUPT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.0 GPIO PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.1 GPIO CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.0 TIMERS/COUNTERS, WATCHDOG TIMER AND PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.1 Timers: T0, T1, T2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.2 Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.2.1 Timer 1 and Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.1 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.2 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.3 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2.1 16-bit Timer/Counter Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2.2 16-bit Timer/Counter Auto-reload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2.3 Baud Rate Generator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 141 141 141 141 142 142 142 142
10.3 Timers/Counters SFRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.4 Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.4.1 Watchdog Timer MMCRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.5 Hibernation Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.6 Pulse Width Modulators (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.6.1 PWM MMCRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.0 SERIAL I/O PORT (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 11.1 Full-Duplex, Enhanced UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
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Advance Information 11.2 Framing Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 11.3 Automatic Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.3.1 Using the Given Address to Select Slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.3.2 Using the Broadcast Address to Select Slaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.4 UART SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.0 SERIAL PERIPHERAL INTERFACE (SPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.1 SPI Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.2 SPI Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.3 SPI Transfer Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.4 SPI SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.0 SMBUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.1 SMBus Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.2 SMBus Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.3 SMBus Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13.4 SMBus MMCRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 13.5 SMBus Multi-master Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.6 Multi-master Bus Address and Data Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 13.7 SMBus Switch Control and Line Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.8 SMBus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.8.1 13.8.2 13.8.3 13.8.4 13.8.5 Master Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Between Master Transmit and Master Receive Modes . . . . . . . . . . . . . . . . . . . . . . 171 173 175 177 179
14.0 PS/2 INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.1 PS/2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.2 PS/2 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.3 PS/2 Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 14.4 PS/2 MMCRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.4.1 14.4.2 14.4.3 14.4.4 14.4.5 PS/2 Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS/2 Receive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS/2 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS/2 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS/2 Time-out and Status 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 183 184 186 189
15.0 FAN TACHOMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.1 Fan Tachometer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.2 Fan Tachometer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.3 Fan Tachometers MMCRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16.0 ANALOG TO DIGITAL CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 16.1 ADC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 16.2 ADC MMCRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.3 ADC Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.3.1 Single Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16.3.2 Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 17.0 DIGITAL TO ANALOG CONVERTOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.1 DAC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.2 DAC MMCRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 17.3 DAC Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 17.3.1 17.3.2 17.3.3 17.3.4 Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAC Channel Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 203 203 204
18.0 KEYBOARD CONTROLLER HOST INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 18.1 Keyboard Controller Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 18.2 Keyboard Controller Interface MMCRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 18.3 Keyboard Matrix Scan Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 19.0 GA20 AND CPU RESET HARDWARE CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 19.1 GA20 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 19.2 GA20 and KBRST# MMCRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 20.0 ACPI EMBEDDED CONTROLLER INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 20.1 ACPI Embedded Controller Interface Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 20.2 Embedded Controller Interface MMCRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 20.3 SMI and SCI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 21.0 MAILBOX INTERFACE AND DATA TRANSFER BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 21.1 Mailbox Command/Data Transfer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 21.2 Mailbox Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 22.0 SERIALIZED INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 22.1 Serialized IRQ Cycle Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 22.2 Serialized IRQ Start Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 22.3 Serialized IRQ Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 22.4 Serialized IRQ Stop Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 23.0 SST79LF008 CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 23.1 Access to Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 23.2 Configuration Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 24.0 ELECTRICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 24.1 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 24.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
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7
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 24.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 24.4 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 24.4.1 24.4.2 24.4.3 24.4.4 24.4.5 24.4.6 24.4.7 24.4.8 LPC Interface and Firmware Memory Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Clocks and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS/2 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM and FAN Tachometer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aLPC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 238 239 240 243 244 247 248
24.5 Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 24.5.1 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 24.5.2 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 25.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 25.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 26.0 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
8
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
LIST OF FIGURES
FIGURE 1-1: SST79LF008 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FIGURE 2-1: Pin Assignments for 176-ball TFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FIGURE 2-2: Pin Assignments for 176-lead LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 FIGURE 3-1: SST79LF008 Program Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FIGURE 3-2: 2 KByte Scratch ROM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FIGURE 3-3: 1 KByte Scratch ROM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FIGURE 3-4: 512 Byte Scratch ROM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FIGURE 3-5: 256 Byte Scratch ROM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FIGURE 3-6: SST79LF008 Data Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FIGURE 4-1: SST79LF008 Flash Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 FIGURE 4-2: Shared ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 FIGURE 4-3: IAP Sector-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 FIGURE 4-4: IAP Block-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 FIGURE 4-5: IAP Word-Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 FIGURE 4-6: IAP Word-Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 FIGURE 4-7: aLPC Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 FIGURE 4-8: aLPC Snooper State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 FIGURE 4-9: aLPC Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 FIGURE 4-10: aLPC Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 FIGURE 4-11: aLPC I/O Write Cycle (IDLE or READY state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 FIGURE 4-12: aLPC I/O Write cycle (SWITCHED state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 FIGURE 5-1: Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 FIGURE 5-2: External Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 FIGURE 5-3: Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 FIGURE 5-4: SST79LF008 Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 FIGURE 5-5: Power-On Sequence and Core Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 FIGURE 5-6: Clock Switching after Waking up from Power Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 76 FIGURE 6-1: Dual Data Pointer Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 FIGURE 7-1: Firmware Memory Read Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 FIGURE 7-2: Firmware Memory Write Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 FIGURE 7-3: LPC Memory Read Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 FIGURE 7-4: LPC Memory Write Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 FIGURE 7-5: LPC I/O Read Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 FIGURE 7-6: LPC I/O Write Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 FIGURE 8-1: SST79LF008 Interrupt Structure (int1-int2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 FIGURE 8-2: SST79LF008 Interrupt Structure (int3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 FIGURE 8-3: SST79LF008 Interrupt Structure (int4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 FIGURE 8-4: SST79LF008 Interrupt Structure (int5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 FIGURE 8-5: SST79LF008 Interrupt Structure (int5, pd mode wakeup, 8051 interrupt) . . . . . . . . . . . . . . 103 FIGURE 10-1: Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 FIGURE 10-2: Hibernation Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
(c)2006 Silicon Storage Technology, Inc. S71320-01-000 10/06
9
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information FIGURE 11-1: Framing Error Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 FIGURE 11-2: UART Timings in Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 FIGURE 11-3: UART Timings in Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 FIGURE 12-1: SPI Master-Slave Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 FIGURE 12-2: SPI Transfer Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 FIGURE 12-3: SPI Transfer Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 FIGURE 13-1: SMBus Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 FIGURE 13-2: SMBus Relationship of SDAn to SCLn for Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 FIGURE 13-3: SMBus Byte Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 FIGURE 13-4: SMBus Address Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 FIGURE 13-5: SMBus Master Transmit Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 FIGURE 13-6: SMBus Master Receive Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 FIGURE 13-7: SMBus Slave Transmit Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 FIGURE 13-8: SMBus Slave Receive Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 FIGURE 13-9: SMBus Transmit/Receive Mode Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 FIGURE 14-1: PS/2 Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 FIGURE 14-2: PS/2 Receive Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 FIGURE 14-3: PS/2 Transmit Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 FIGURE 15-1: Fan Tachometer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 FIGURE 16-1: ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 FIGURE 16-2: Example of ADC Operation (Single Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 FIGURE 16-3: Example of ADC Operation (Continuous Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 FIGURE 17-1: DAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 FIGURE 18-1: KBC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 FIGURE 19-1: GA20 State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 FIGURE 19-2: : Host and 8051 Control of GA20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 FIGURE 20-1: SCI and SMI Generation Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 FIGURE 22-1: Serialized IRQ cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 FIGURE 24-1: AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 FIGURE 24-2: A Test Load Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 FIGURE 24-3: LCLK Wave Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 FIGURE 24-4: LPC Output Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 FIGURE 24-5: LPC Input Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 FIGURE 24-6: LPC Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 FIGURE 24-7: External Input Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 FIGURE 24-8: External Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 FIGURE 24-9: Power Up and External Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 FIGURE 24-10: SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 FIGURE 24-11: PS/2 Hardware State Machine Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 240 FIGURE 24-12: PS/2 Hardware State Machine Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 240 FIGURE 24-13: PS/2 Interrupt Timing in bit-banging mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 FIGURE 24-14: UART Timing Diagram (Shift Register Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 FIGURE 24-15: SPI Master Timing Diagram (CPHA=0, MSTR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
(c)2006 Silicon Storage Technology, Inc. S71320-01-000 10/06
10
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information FIGURE 24-16: SPI Master Timing Diagram (CPHA=1, MSTR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 FIGURE 24-17: SPI Slave Timing Diagram (CPHA=0, MSTR = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 FIGURE 24-18: SPI Slave Timing Diagram (CPHA=1, MSTR = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 FIGURE 24-19: PWM Output Signals Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 FIGURE 24-20: FAN Tachometer Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 FIGURE 24-21: aLPC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 FIGURE 26-1: 176-lead Low-profile Quad Flat Pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 FIGURE 26-2: 176-ball Thin-profile Fine-pitch Ball Grid Array (TFBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . 252
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
11
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
LIST OF TABLES
TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TABLE 2-2: I/O Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TABLE 3-1: Special Function Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 TABLE 3-2: Miscellaneous SFRs Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TABLE 3-3: Timer SFRs Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TABLE 3-4: UART SFRs References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TABLE 3-5: SPI SFRs References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TABLE 3-6: GPIO Input MMCRs References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TABLE 3-7: GPIO Output MMCRs References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TABLE 3-8: GPIO Direction MMCRs References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TABLE 3-9: GPIO Function Selection MMCRs References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TABLE 3-11: Interrupt Source MMCRs References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 TABLE 3-10: GPIO Active Edge Selection MMCRs References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 TABLE 3-12: Wakeup Source MMCRs References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TABLE 3-13: Timer MMCRs References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TABLE 3-14: PWM MMCRs References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TABLE 3-15: SMBus MMCRs References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TABLE 3-16: PS/2 MMCRs References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TABLE 3-17: Fan Tachometer MMCRs References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TABLE 3-18: ADC MMCRs References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TABLE 3-19: DAC MMCRs References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TABLE 3-20: KBC Host Interface MMCRs References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TABLE 3-21: GA20 Control MMCRs References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TABLE 3-22: ACPI EC Interface MMCRs References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TABLE 3-23: MailBox MMCRs References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 TABLE 3-24: Configuration MMCRs References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TABLE 3-25: Miscellaneous MMCRs References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TABLE 4-1: ENVR Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 TABLE 4-2: UNVR Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 TABLE 4-3: Scratch ROM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 TABLE 4-4: IAP Commands for SST79LF008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TABLE 4-5: OVERLAY Bit Value After RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 TABLE 4-6: aLPC Snooper Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 TABLE 4-7: aLPC Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 TABLE 4-8: aLPC Memory Write Cycle Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 TABLE 4-9: aLPC Memory Read Cycle Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 TABLE 4-10: aLPC I/O Write Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 TABLE 4-11: aLPC Bus Flash Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TABLE 5-1: SST79LF008 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 TABLE 5-2: SST79LF008 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 TABLE 5-3: Crystal Oscillator Circuit Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
(c)2006 Silicon Storage Technology, Inc. S71320-01-000 10/06
12
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 5-4: Clock Domains for SST79LF008 Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 TABLE 6-1: 17-bit Addressing Mode-Specific Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 TABLE 7-1: Transfer Size Supported by the SST79LF008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 TABLE 7-2: Firmware and LPC Memory Cycles START Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . 82 TABLE 7-3: Firmware Memory Read Cycle Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 TABLE 7-4: Firmware Memory Write Cycle Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 TABLE 7-5: LPC Memory Read Cycle Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 TABLE 7-6: LPC Memory Write Cycle Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 TABLE 7-7: LPC I/O Read Cycle Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 TABLE 7-8: LPC I/O Write Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 TABLE 7-9: LPC Flash Command Definitions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 TABLE 7-10: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 TABLE 7-11: Valid MSIZE Field for Firmware Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 TABLE 7-12: Block Locking Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 TABLE 7-13: Block Locking Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 TABLE 7-14: JEDEC ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 TABLE 7-15: Multi-byte Read/Write Configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 TABLE 7-16: Unique ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 TABLE 8-1: SST79LF008 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 TABLE 9-1: LPC Host Status Signals as a Function of SSEL[2:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 TABLE 9-2: GPIO96-GPIO111 Input/Output configuration control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 TABLE 10-1: Timer 0 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 TABLE 10-2: Timer 1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 TABLE 10-3: Timer 2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 TABLE 10-4: Timer/Counters SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 TABLE 10-5: Timer Operating Mode as a Function of Mode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 TABLE 10-6: LED 4/2/0 Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 TABLE 10-7: LED 3/1 Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 TABLE 11-1: Possible Addresses for Slaves 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 TABLE 11-2: Possible Addresses for Slave 3 and Slave 2/3 Combination . . . . . . . . . . . . . . . . . . . . . . . 156 TABLE 11-3: Serial Port Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 TABLE 12-1: SCK Rate as a Function of SPI Clock Rate Select Bits (Master Only) . . . . . . . . . . . . . . . . 161 TABLE 12-2: SCK Rate as a Function of SPI Clock Rate Select Bits (Slave Only) . . . . . . . . . . . . . . . . . 162 TABLE 13-1: SMBus MMCRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 TABLE 16-1: Analog Input Channels/Data Registers relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 TABLE 16-2: Channel and Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 TABLE 18-1: Keyboard Controller Interface Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 TABLE 18-2: KBC Output Buffer Flags Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 TABLE 18-3: KBC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 TABLE 18-4: Mouse Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 TABLE 18-5: KSO[15:0] Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 TABLE 19-1: GA20 Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 TABLE 20-1: Embedded Controller Interface Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
(c)2006 Silicon Storage Technology, Inc. S71320-01-000 10/06
13
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 21-1: Mailbox Command/Data Transfer Registers Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 TABLE 21-2: Mailbox Control Registers Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 TABLE 22-1: SST79LF008 SERIRQ Sampling Periods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 TABLE 23-1: Configuration Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 TABLE 24-1: Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 TABLE 24-2: AC Condition of Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 TABLE 24-3: Recommended System Power-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 TABLE 24-4: Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 TABLE 24-5: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 TABLE 24-6: DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 TABLE 24-7: LPC Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 TABLE 24-8: LPC Read/Write Cycle Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 TABLE 24-9: LPC AC Input/Output Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 TABLE 24-10: LPC Interface Measurement Condition Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 TABLE 24-11: LPC Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 TABLE 24-12: External Clocks and Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 TABLE 24-13: SMBus Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 TABLE 24-14: SMBus Interface Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 TABLE 24-15: PS/2 Receive Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 TABLE 24-16: PS/2 Transmit Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 TABLE 24-17: PS/2 Interrupt Timing in bit-banging mode, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 TABLE 24-18: PS/2 Interface Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 TABLE 24-19: UART Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 TABLE 24-20: SPI Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 TABLE 24-21: PWM Output Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 TABLE 24-22: FAN Tachometer Input Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 TABLE 24-23: aLPC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 TABLE 24-24: ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 TABLE 24-25: DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 TABLE 26-1: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
14
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
1.0 FUNCTIONAL BLOCKS
FWH/LPC/aLPC Memory Interface LPC I/O Host Interface
Shared-ROM Interface
Enhanced 8051 Core
GPIOs
Flash Memory
Host Interface Configuration Keyboard Controller Ports 2 sets ACPI Embedded Controller Ports 32 Byte-wide Mailbox Registers (8 Mbit main array + 32 Kbit ENVR +24 Kbit UNVR) 5 LED Drivers
16x8 Keyboard Matrix Interface
Timer 0, 1, 2
3 PWM channels
2 KByte Expanded RAM
(XRAM) or
Hibernation Timer
Watchdog Timer
UART
Scratch ROM
3 PS/2 Ports
SPI
256 Byte Data RAM
CLOCK, RESET, and Power Mode Control Blocks
3 SMBus channels (2 controllers) 8-channel 10-bit resolution ADC 4-channel 8-bit resolution DAC 2-channel FAN tachometer
1245 B1.1
FIGURE
1-1: SST79LF008 Functional Block Diagram
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
15
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
2.0 PIN ASSIGNMENTS
The signal/pin assignments are listed in Table 2-1. Low active signals have a "#" suffix. I/O buffer types are listed in Table 2-2. Section 24.0 defines the DC characteristics for all input and output buffers.
TOP VIEW (balls facing down)
14
KSO0 KSO2 KSO5 KSO9 KSO13 GPIO105 GPIO109 P11 P15 PWM1 PWM2 MISO
13
ID KSO1 KSO3 KSO6 KSO10 KSO14 GPIO106 GPIO110 P12 P16 OSC1 MOSI SCK RESET#
12
GPIO66 GPIO67 KSO4 KSO7 KSO11 KSO15 GPIO107 GPIO111 P13 P17 OSC2 GA20 SS# PWRGOOD
11
GPIO63 GPIO64 GPIO65 KSO8 KSO12 GPIO104 GPIO108 P10 P14 PWM0 aLAD GPIO42 GPIO41 EC1_SCI#
10
GPIO59 GPIO60 GPIO61 GPIO62 VSS VDD VSS VDD VSS VDD SS1 T1 aFRAME# aLCLK
9
GPIO55 GPIO56 GPIO57 GPIO58 VDD VSS LED1 LED0 T2EX SS2
8
SDA0 SCL0 RXD TXD VSS VSS GPIO95 GPIO94 LED3 LED2
7
LAD3 LCLK LPCPD# 32KOUT VDD VDD SMI# LED4 GPIO97 GPIO96
6
LAD0 LAD1 LAD2 VDD VSS VSS FAN2 FAN1 GPIO23 EC_SCI#
5
LRESET# SERIRQ LFRAME# VDD VSS VDD VDD VSS VSS VDD VDD PSCLK0 SDA2 SCL2
4
VREG CLKRUN# AVDD VSS ACH5 ACH1 T2 GPIO9 GPIO101 KSI13 KSI9 PSDAT1 PSCLK1 PSDAT0
3
AVDD AVSS VSS DAC3 ACH4 ACH0 SS0 GPIO8 GPIO100 KSI12 KSI8 KSI5 PSDAT2 PSCLK2
2
AVSS VSS DAC1 ACH7 ACH3 CLKOUT KBRST# GPIO103 GPIO99 KSI11 KSI7 KSI4 KSI1 KSI0
1
DAC0 DAC2 ACH6 ACH2 WDOUT ECLK GPIO102 GPIO98 KSI10 KSI6 KSI3 KSI2
A
FIGURE
B
C
D
E
F
G
H
J
K
L
M
N
P
1245176-tfbga P2.1
2-1: Pin Assignments for 176-ball TFBGA
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
16
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VDD DAC0/GPIO68 DAC1/GPIO69 DAC2/GPIO70 DAC3/GPIO71 ACH7/GPIO72 ACH6/GPIO73 ACH5/GPIO74 ACH4/GPIO75 ACH3/GPIO76 ACH2/GPIO77 ACH1/GPIO78 ACH0/GPIO79 CLKOUT/GPIO49 WDOUT/GPIO48 T2/GPIO47 SS0#/GPIO12 KBRST#/GPIO11 ECLK/GPIO10 GPIO9 GPIO8 GPIO103 GPIO102 VDD VSS GPIO101 GPIO100 GPIO99 GPIO98 KSI13/GPIO85 KSI12/GPIO84 KSI11/GPIO83 KSI10/GPIO82 KSI9/GPIO81 KSI8/GPIO80 KSI7 KSI6 KSI5 KSI4 KSI3 KSI2 VSS VDD VDD 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
VSS AVSS AVSS AVDD AVDD VREG VDD VSS VSS CLKRUN#/GPIO39 LRESET# SERIRQ LFRAME# LAD0 LAD1 VSS VSS VDD VDD LAD2 LAD3 LCLK LPCPD#/GPIO38 VSS VDD 32KOUT/GPIO50 SDA0/GPIO51 SCL0/GPIO52 RXD/SDA1/GPIO53 TXD/SCL1/GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66 GPIO67 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
VDD ID KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12/GPIO34 KSO13/GPIO35 KSO14/GPIO36 KSO15/GPIO37 GPIO104 GPIO105 GPIO106 GPIO107 GPIO108 GPIO109 GPIO110 GPIO111 P10/GPIO86 P11/GPIO87 P12/GPIO88 P13/GPIO89 P14/GPIO90 P15/GPIO91 P16/GPIO92 P17/GPIO93 PWM0/GPIO0 PWM1/GPIO1 VSS OSC1 OSC2 VDD PWM2/GPIO2 MOSI/GPIO3 MISO/GPIO4 SCLK/GPIO5
KSI1 KSI0 PSDAT2/GPIO33 PSCLK2/GPIO32 PSDAT1/GPIO31 PSCLK1/GPIO30 PSDAT0/GPIO29 PSCLK0/GPIO28 SDA2/GPIO27 SCL2/GPIO26 VSS FAN2/GPIO25 FAN1/GPIO24 VDD VSS GPIO23 EC_SCI#/GPIO22 SMI#/GPIO21 LED4/GPIO20 GPIO97 GPIO96 VDD VSS VSS GPIO95 GPIO94 LED3/GPIO19 LED2/GPIO18 LED1/GPIO17 LED0/GPIO16 T2EX/GPIO15 SS2/GPIO14 SS1/GPIO13 T1/GPIO46 T0/GPI45/aLFRAME# GPI44/aLCLK GPI43/aLAD GPIO42 GPIO41 EC1_SCI#/GPIO40 GA20/GPIO7 SS#/GPIO6 PWRGOOD RESET#
1245 176-lqfp LRR P1.0
FIGURE
2-2: Pin Assignments for 176-lead LQFP
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
17
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
2.1 Pin Descriptions
The pins and functions of each pin in Table 2-1 are organized by each pin's major function. However, some pins are multiplexed with GPIO function. TABLE
Symbol LPC Bus Interface(10) LAD3 LAD2 LAD1 LAD0 LCLK LFRAME# IPCI IPCI IOPCI 156 157 162 163 155 164 A7 C6 B6 A6 B7 C5 1 1 LPC Clock: LPC bus clock input signal (commonly the same as PCI clock, up to 33MHz) LPC Frame: LPC bus control input signal. Low pulse indicates the start of the LPC transfer cycle when the bus is idle, or the termination (abort) of the broken LPC cycle already in progress. LPC Power Down: LPC Power down input signal, or GPIO Port. Indicates that power will be removed from the LPC bus. Clock Run: PCI Clock Control signal, or GPIO Port. Indicates when LPC clock is (about to be) stopped by the LPC host, and provides a mechanism for the LPC device to request clock re-start. LPC Reset: LPC bus reset input signal. This signal is used to reset the LPC interface control logic. Serialized IRQ: This signal is used to generate serialized interrupts from the SST79LF008 to the LPC host. KSO[15:12] Keyboard Scan Outputs: Keyboard Scan output pins, or GPIO Port 4 LPC Address/Data bus LAD[3:0]: Multiplexed command, address and data bi-directional bus signals.
2-1: Pin Descriptions (1 of 6)
I/O Buffer Type 176-leads or balls LQFP TFBGA Number of pins Name and Functions
LPCPD# / GPIO38
IOD6
154
C7
1
CLKRUN# / GPIO39
IODPCI
167
B4
1
LRESET#
IPCI
166
A5
1
SERIRQ
IOPCI
165
B5
1
Keyboard Matrix Interface (30) KSO15/GPIO37 KSO14/GPIO36 KSO13/GPIO35 KSO12/GPIO34 IOD4 115 116 117 118 F12 F13 F14 E11 4
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Advance Information TABLE
Symbol KSO11 KSO10 KSO9 KSO8 KSO7 KSO6 KSO5 KSO4 KSO3 KSO2 KSO1 KSO0 KSI13/GPIO85 KSI12/GPIO84 KSI11/GPIO83 KSI10/GPIO82 KSI9/GPIO81 KSI8/GPIO80 KSI7 KSI6 KSI5 KSI4 KSI3 KSI2 KSI1 KSI0 PS/2 Interface (6) PSDAT2/GPIO33 PSDAT1/GPIO31 PSDAT0/GPIO29 PSCLK2/GPIO32 PSCLK1/GPIO30 PSCLK0/GPIO28 SMBus and UART Interface (6) SDA0/GPIO51 SCL0/GPIO52 RXD/SDA1/GPIO53 TXD/SCL1/GPIO54 SDA2/GPIO27 SCL2/GPIO26 SIO6 SIO6 SIO6 SIO6 SIO6 SIO6 150 149 148 147 53 54 A8 B8 C8 D8 N5 P5 1 1 1 1 1 1 SMBus: Channel 0 data signal, or GPIO port SMBus: Channel 0 clock signal, or GPIO port UART: Receive data input, or SMBus channel 1 data signal, or GPIO port UART: Transmit data output, or SMBus channel 1 clock signal, or GPIO port SMBus: Channel 2 data signal, or GPIO port SMBus: Channel 2 clock signal, or GPIO port SIOD15 SIOD15 47 49 51 48 50 52 N3 M4 P4 P3 N4 M5 3 PSCLK[2:0] PS/2: Channel 2 to 0 clock signal, or GPIO Port 3 PSDAT[2:0] PS/2:Channel 2 to 0 data signal, or GPIO Port SI_PU SIO4_PU
2-1: Pin Descriptions (Continued) (2 of 6)
I/O Buffer Type OD4 176-leads or balls LQFP 119 120 121 122 123 124 125 126 127 128 129 130 30 31 32 33 34 35 36 37 38 39 40 41 45 46 TFBGA E12 E13 E14 D11 D12 D13 D14 C12 C13 C14 B13 B14 K4 K3 K2 K1 L4 L3 L2 L1 M3 M2 M1 N1 N2 P2 8 KSI[7:0] Keyboard Scan Inputs: 8 Keyboard Scan input pins with internal pullup resistors and wake up interrupts (pull-ups are always enabled). 6 KSI[13:8] Extended Keyboard Scan Inputs: 6 individually selectable Keyboard Scan input pins (with internal pull-ups and wake up interrupts). Each of these pins can be also configured as GPIO with programmable pull-up resistors (disabled after reset). Number of pins 12 Name and Functions KSO[11:0] Keyboard Scan Outputs: Keyboard Scan output pins only
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Advance Information TABLE
Symbol SPI interface (4) MOSI/GPIO3 MISO/GPIO4 SCK/GPIO5 SS#/GPIO6 IO5 IO5 IO5 IO5 91 90 89 86 M13 N14 N13 N12 1 1 1 1 SPI Data: Master data output line, slave data Input line, or GPIO port SPI Data: Master data input line, slave data output line, or GPIO Port SPI Clock: Master clock output line, slave clock input line, or GPIO Port SPI Port Select: Slave port select input, or GPIO Port aLPC DATA: Alternative LPC Address/Data Bus or GPI Port aLPC Clock: Alternative LPC clock or GPI Port Timer0 Counter Input: External count input to Timer/Counter 0, or GPI Port, or aLPC frame: alternative LPC Frame Timer1 Counter Input or Output: External count input to Timer/Counter 1, or Clock output from Timer/Counter 1, or GPIO Port Timer2 Counter Input or Output: External count input to Timer/Counter 2, or Clock output from Timer/Counter 2, or GPIO Port Watchdog Timer Output: Watchdog Timer Output, or GPIO Port Timer 2 External Input: External interrupt input to Timer 2, or GPIO Port PWM[2:0] PWM Output: PWM output 2 to 0, or GPIO Port
2-1: Pin Descriptions (Continued) (3 of 6)
I/O Buffer Type 176-leads or balls LQFP TFBGA Number of pins Name and Functions
aLPC bus, Timers, PWMs and Fan Tachometers (12) GPI43/aLAD GPI44/aLCLK T0/GPI45/aLFRAME# AIO4 AIO4 IO5 81 80 79 L11 P10 N10 1 1 1
T1/GPIO46
IO5
78
M10
1
T2/GPIO47
IO5
16
G4
1
WDOUT/GPIO48 T2EX/GPIO15 PWM2/GPIO2 PWM1/GPIO1 PWM0/GPIO0 FAN2/GPIO25 FAN1/GPIO24 LED Drivers (5) LED4/GPIO20 LED3/GPIO19 LED2/GPIO18 LED1/GPIO17 LED0/GPIO16
IO5 IO5 IO5
15 75 92 97 98
F1 N9 M14 L14 K11 L6 M6 M7 N8 P8 L9 M9
1 1 3
SIO6
56 57
2
FAN[2:1] Fan Input: Fan Tachometer input 2 to 1, or GPIO port
SIOD15
63 71 72 73 74
5
LED[4:0] LED Driver output, or GPIO Port
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Advance Information TABLE
Symbol EC1_SCI#/GPIO40
2-1: Pin Descriptions (Continued) (4 of 6)
I/O Buffer Type SIOD15 176-leads or balls LQFP 84 TFBGA P11 Number of pins 1 Name and Functions Embedded Controller Interrupt: Embedded controller interrupt output for port 68H/6CH Host interface, or GPIO Port System Management Interrupt: System management interrupt output, or GPIO Port Embedded Controller Interrupt: Embedded controller interrupt output for port 62H/66H Host interface, or GPIO Port GPIO Port Gate A20: GA20 output, or GPIO Port KBC Reset to CPU: Keyboard Controller reset output, or GPIO Port SS[2:0] LPC Host Status Signals: LPC IO Host interface status signal output, or GPIO Port GPIO Port
Miscellaneous and Dedicated GPIOs (52)
SMI#/GPIO21 EC_SCI#/GPIO22
SIOD15 SIOD15
62 61
L7 P6
1 1
GPIO23 GA20/GPIO7 KBRST#/GPIO11 SS2/GPIO14 SS1/GPIO13 SS0/GPIO12 GPIO8 GPIO9 GPIO41 GPIO42 GPIO55 GPIO67 GPIO66 GPIO65 GPIO64 GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56 P17/GPIO93 P16/GPIO92 P15/GPIO91 P14/GPIO90 P13/GPIO89 P12/GPIO88 P11/GPIO87 P10/GPIO86
SIO6 IO5 IO5 IO5
60 85 18 76 77 17
N6 M12 G2 P9 L10 G3 H3 H4 N11 M11 A9 B12 A12 C11 B11 A11 D10 C10 B10 A10 D9 C9 B9 K12 K13 K14 J11 J12 J13 J14 H11
1 1 1 3
IO5 IO5 IO5 IO5 SIO6 IO5
21 20 83 82 146 134 135 136 137 138 139 140 141 142 143 144 145
5
12
GPIO Port
IO5
99 100 101 102 103 104 105 106
8
P[17:10] 8051 Port1 or GPIO Port
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Advance Information TABLE
Symbol GPIO111 GPIO110 GPIO109 GPIO108 GPIO107 GPIO106 GPIO105 GPIO104 GPIO103 GPIO102 GPIO101 GPIO100 GPIO99 GPIO98 GPIO97 GPIO96 GPIO95 GPIO94 Analog Interface (12) DAC3/GPIO71 DAC2/GPIO70 DAC1/GPIO69 DAC0/GPIO68 ACH7/GPIO72 ACH6/GPIO73 ACH5/GPIO74 ACH4/GPIO75 ACH3/GPIO76 ACH2/GPIO77 ACH1/GPIO78 ACH0/GPIO79 Clocks (5) OSC1 OSC2 OSC 95 94 L13 L12 1 1 OSC1 and OSC2: Input and Output of the internal inverting oscillator amplifier. These 2 pins are connected to the external 32.768KHz crystal circuit. 32KHz Clock: Output of 32.768Khz clock signal, or GPIO Port ECLK: External Clock input, or GPIO Port Core Clock Output: 8051 core clock output, or GPIO Port AIO4 AIO4 5 4 3 2 6 7 8 9 10 11 12 13 D3 C1 C2 B1 D2 D1 E4 E3 E2 E1 F4 F3 8 ACH[7:0] ADC: Analog to Digital Converter input, or GPIO Port 4 DAC[3:0] DAC: Digital to Analog Converter outputs, or GPIO Port
2-1: Pin Descriptions (Continued) (5 of 6)
I/O Buffer Type SIO4_PU 176-leads or balls LQFP 107 108 109 110 111 112 113 114 22 23 26 27 28 29 64 65 69 70 TFBGA H12 H13 H14 G11 G12 G13 G14 F11 H2 H1 J4 J3 J2 J1 N7 P7 L8 M8 Number of pins 18 Name and Functions GPIO Port: with internal programmable pullup resistors (enabled after reset).
32KOUT/GPIO50 ECLK/GPIO10 CLKOUT/GPIO49
IO5 IO5 IO5
151 19 14
D7 G1 F2
1 1 1
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Advance Information TABLE
Symbol PWRGOOD RESET#
2-1: Pin Descriptions (Continued) (6 of 6)
I/O Buffer Type I SI_PU 176-leads or balls LQFP 87 88 TFBGA P12 P13 Number of pins 1 1 Name and Functions Power Good: Input used to select clock source Reset: By setting the RESET# pin low, the entire device is reset to a default state (internal pull-up resistor always enabled). Firmware Memory ID: LPC Firmware memory ID selection input (internal pull-down resistor always enabled). Digital Power supply 3.3V: (power supply voltage must be applied to all VDD pins) Analog Power Supply 3.3V: (analog power supply voltage must be applied to all AVDD pins) Ground (GND): 0V reference (ground plane must be connected to all VSS pins)
Reset, ID and Power (34)
ID
I_PD
131
A13
1
VDD
PWR
1, 24, 43, 44 58, 66, 93, 132, 152, 158, 159, 170 172,173
F5, G5, K5, L5, K7, K10, H10, F10, E9, E7, D6, D5 C4, A3
12
AVDD
PWR
2
VSS
PWR
25, 42, 55, H5, J5, K6, 59, 67, 68, K8, K9, J10, 96, 133, 153, G10, E10, E8, 160, 161, 168, E6, E5, D4, 169, 176 C3, B2 174, 175 B3, A2
14
AVSS
PWR
2
Analog Ground: For ADC and DAC (analog ground plane must be connected to all AVSS pins as well as to GND plane) Internal voltage regulator output: An external ceramic capacitor (1f) must be connected between this pin and system ground.
T2-1.1 1320
VREG
PWR
171
A4
1
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Advance Information
2.2 I/O Type Descriptions
I/O buffer types in Table 2-1 are described in Table 2-2. DC parameters are described in Section 24.0. TABLE
AIO4 I I_PD IO5 IOD4 IOD6 IODPCI IOPCI IPCI OSC OD4 SI_PU SIO4_PU SIO6 SIOD15 PWR
2-2: I/O Buffer Types1
Description I/O with push-pull 4mA output multiplexed with Analog function Input Input with internal pull-down I/O with push-pull 5mA output Input, open drain output with 4mA sink capability Input, open drain output with 6mA sink capability Input, open drain output, PCI compatible I/O, PCI compatible Input, PCI compatible 32 kHz oscillator input and output Open drain output with 4mA sink capability Schmitt triggered input with internal pull-up I/O with Schmitt triggered input, push-pull 4mA output, internal pull-up I/O with Schmitt triggered input, push-pull 6mA output Schmitt triggered input, open drain output with 15mA sink capability Power or Ground pin
T2-2.1 1320
I/O Buffer Type
1. Any pin configured as input or OD high output without internal pull-up or pull-down resistor must not be left disconnected.
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3.0 MEMORY ORGANIZATION
The on-chip 8051 MCU has separate address spaces for program and data memory, which are described in this section. The on-chip 8051 can also access, via Shared ROM Interface, a total of 1 MByte (8 Mbits) of the main Flash Memory array, 4 KByte of ENVR flash sector, and 3 KBytes of UNVR one-time programmable memory. The main Flash Memory array is divided into 16 blocks with 64 KByte block size, each block consists of 16 sectors with 4 KByte sector size. The entire main array as well as ENVR can be erased/programmed/read by the 8051 core using in-application programming mode commands specified in Section 4.0. However, only the two bottom blocks of the main array can be mapped into 8051 program space. to 128 KByte. Flash memory Block 0 is mapped to 8051 program memory to store firmware code in 16-bit addressing mode, and Flash memory Blocks 0 and 1 are mapped to 8051 program memory to store firmware code in 17-bit addressing mode. For program memory organization, see Figure 3-1. The addressing mode is controlled by ACON register, described in Section 6.5. Additionally, sections of the on-chip SRAM can be mapped into the 8051 program space providing a so called Scratch ROM area for code that can run during in-application programming. The size of Scratch ROM can be selected as 2 KByte, 1 KByte, 512 Byte, or 256 Byte. See Figures 3-2, 33, 3-4, and 3-5. Scratch ROM mapping and size is controlled by SCRROM register, defined in Section 4.4.1.
3.1 Program Memory
The SST79LF008 enhanced 8051 MCU can operate either in 16-bit addressing mode with firmware size up to 64 KByte, or in 17-bit addressing mode with firmware size up
Physical Flash
FFFFFH Block 15 EFFFFH Block 14 E0000H
Blocks 13-2
8051 Program Space 1FFFFH Block 1 0FFFFH 00000H
1245 PgmMemOrg.0
1FFFFH 8051 Code Size 128 KB only 0FFFFH Block 0 8051 Code Size 64 KB or 128 KB 00000H
FIGURE
3-1: SST79LF008 Program Memory Organization
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1FFFFH
8051 Program Space
8051 External Data Memory Space
FFFFH
2 KByte SRAM mapped to external data memory space can be remapped to top or bottom of Block 0 in program space and become Scratch ROM Memory Mapped Registers
7FFFH
7F00H 0FFFFH 2 KByte 0F800H
64 KByte 07FFH 007FFH 2 KByte 2 KByte 00000H
1245 2KScrROMmap.0
0000H
FIGURE
3-2: 2 KByte Scratch ROM Mapping
1FFFFH
8051 Program Space
8051 External Data Memory Space
FFFFH
1 KByte SRAM mapped to external data memory space can be remapped to top or bottom of Block 0 in program space and become Scratch ROM Memory Mapped Registers
7FFFH
7F00H 0FFFFH 1 KByte 0FC00H
64 KByte
07FFH 1 KByte 0400H
003FFH 1 KByte 00000H 1 KByte
1245 1KScrROMmap.0
0000H
FIGURE
3-3: 1 KByte Scratch ROM Mapping
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1FFFFH
8051 Program Space
8051 External Data Memory Space
FFFFH
512 Byte SRAM mapped to external data memory space can be remapped to top or bottom of Block 0 in program space and become Scratch ROM Memory Mapped Registers
7FFFH
7F00H 0FFFFH 512 Byte 0FE00H
64 KByte
07FFH 512 Kyte 0600H
001FFH 1,536 Byte 00000H 512 Byte
1245 512BScrROMmap.0
0000H
FIGURE
3-4: 512 Byte Scratch ROM Mapping
1FFFFH
8051 Program Space
8051 External Data Memory Space
FFFFH
256 Byte SRAM mapped to external data memory space can be remapped to top or bottom of Block 0 in program space and become Scratch ROM Memory Mapped Registers
7FFFH
7F00H 0FFFFH 256 Byte 0FF00H
64 KByte
07FFH 256 Kyte 0700H
000FFH 1,792 Byte 00000H 256 Byte
1245 256BScrROMmap.0
0000H
FIGURE
3-5: 256 Byte Scratch ROM Mapping
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3.2 Data Memory
The on-chip 2304-Byte SRAM can be divided into three sections: 1. Lower RAM - SRAM section mapped to the lower 128 Bytes of 8051 Internal Data Memory space (00H to 7FH), that are directly and indirectly addressable. 2. Upper RAM - SRAM section mapped into the higher 128 Bytes of 8051 Internal Data Memory space (80H to FFH), that are indirectly addressable only. 3. Expanded RAM - SRAM section mapped into 2048 bytes of 8051 External Data Memory space (0000H to 07FFH) that are indirectly addressable via 8051 external memory access instructions only. (As described in Section 3.1, 256, 512, 1024 or 2048 Bytes of this SRAM section can be also remapped to the 8051 program address space providing a Scratch ROM area.) The on-chip Special Function Registers (SFRs) are mapped into the higher 128 Bytes of 8051 Internal Data Memory space (80H to FFH), and thus overlapped with Upper RAM. However, unlike Upper RAM, all SFRs are directly addressable only. The on-chip Memory Mapped Configuration registers (MMCRs) are mapped into 256 bytes of 8051 External Data Memory space (7F00H to 7FFFH) that are indirectly addressable via 8051 external memory access instructions only.
8051 External Data Memory Space (Indirect X Addressing)
FFFFH
7FFFH
7F00H
Memory Mapped Configuration Registers (MMCRs)
07FFH
8051 Internal Data Memory Space
FFH (Indirect Addressing) FFH (Direct Addressing) Special Function Registers (SFRs)
Expanded RAM 2 KByte
80H 7FH
Upper 128 Bytes Internal RAM Lower 128 Bytes Internal RAM
80H
0000H
00H
(Indirect and Direct Addressing)
1245 DataMemOrg.0
FIGURE
3-6: SST79LF008 Data Memory Organization
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3.3 Data Memory Addressing Modes
The Lower RAM is accessed by all 8051 instructions that utilize both direct and indirect internal data memory addressing modes. In addition the lowest 32 bytes (00H1FH) of Lower RAM are grouped into 4 banks of 8 registers, which can be accessed by 8051 register addressing mode. Bytes 20H-2FH provide a 128-bit addressable space, accessible by 8051 bit addressing mode (bit addresses 00H-7FH). Because the Upper RAM occupies the same addresses as the SFRs, the respective data areas are distinguished by the type of addressing mode used: the Upper RAM is accessed via indirect internal data memory addressing mode, and the SFRs are accessed via direct internal data memory addressing mode. The SFRs that are located at addresses ended with 0H or 8H are also bit-addressable (bit addresses 80H-FFH). The entire Expanded RAM and MMCRs are accessed by 8051 MOVX instructions that utilize indirect external data memory addressing mode and DPTR pointer. Using MOVX with R0/R1 indirect pointer can only access the lowest 256 bytes of total 2KB Expanded RAM. 3.4.1 SFR Map TABLE
F8H F0H E8H E0H D8H D0H C8H C0H B8H B0H A8H A0H 98H 90H 88H 80H IP1 P31 IE1 P21 SCON1 P11 TCON1 P01 TMOD SP TL0 DPL SBUF SADDR SPSR AUXR1 ESP DPX TL1 DPH TH0 TH1 SPDR PCON ACON EXIF SADEN IPH CLKCON PSW1 T2CON1 T2MOD RCAP2L RCAP2H TL2 SPCR TH2
The 8051 stack with default 8-bit addressing mode can be located anywhere within the 256 bytes of Lower and/or Upper RAM. For additional details on 8051 addressing modes refer to the description of standard 8051 instruction set. For the SST79LF008 enhanced 8051 MCU features, see Section 6.0.
3.4 Special Function Registers (SFRs)
All Special Function Registers are located in 8051 internal data memory space, addresses 80H - FFH. For the detailed description of SFRs see the respective sections as specified in Tables 3-2, 3-3, 3-4, and 3-5. Some of SFRs contain reserved bits. On reads, software must not rely on reserved bits being any particular value. On writes, zeros should be written to reserved bits. When modifying a register with reserved bits the values read from the reserved bits can be written back to them. Software should not write to non used locations in SFR space.
3-1: Special Function Register Memory Map
8 BYTES IPA1 B1 IEA1 ACC1 IPAH FFH F7H EFH E7H DFH D7H CFH C7H BFH B7H AFH A7H 9FH 97H 8FH 87H
T3-1.0 1320
1. Bit addressable SFRs
Function and bit definitions for registers ACC, B, PSW, and P1 are the same as in standard 8051 MCU. Registers P0, P2, P3 are reserved. For the detailed description of all other SFRs see the respective sections as specified in the reference charts below.
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Advance Information 3.4.2 SFR References TABLE 3-2: Miscellaneous SFRs Reference
Bit Access Type Register Name P1 PSW ACC B CLKCON EXIF IE IEA IP IPH IPA IPAH AUXR1 ACON SP ESP DPL DPH DPX Address 90H D0H E0H F0H AFH ABH A8H E8H B8H B7H F8H F7H A2H 9DH 81H 9BH 82H 83H 93H Reference Section 6.3.1 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 6.4.1 6.5.1 6.5.3 6.5.2 6.4.2 6.4.3 6.4.4 7 Q 6 R 5 4 3 2 R 1 Q 0 R Reset Value1 00H 00H 00H 00H xxxx0100b x0H 0x000000b x0H 0x000000b 0x000000b x0H x0H xxxxxxx0b xxxxx00xb 07H xxxxx000b 00H 00H xxxxxxx0b
T3-2.0 1320
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
QQQQQQQQ QQQ QQQQQQQQ QQQQQQQQ Q Q Q QQQQ R R R R
QQQQQQ QQQQ QQQQQQ QQQQQQ QQQQ QQQQ Q QQ
QQQQQQQQ QQQ QQQQQQQQ QQQQQQQQ Q
1. All SFRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
TABLE
3-3: Timer SFRs Reference
Bit Access Type Address 88H 89H 8AH 8BH 8CH 8DH C8H C9H CAH CBH CCH CDH Reference Section 10.3.1 10.3.2 10-1 10-1 10-1 10-1 10.3.3 10.3.4 10-1 10-1 10-1 10-1 7 R 6 5 4 3 R R 2 R 1 R 0 R Reset Value1 00H 00H 00H 00H 00H 00H 00H x0H 00H 00H 00H 00H
T3-3.0 1320
Register Name TCON TMOD TL0 TL1 TH0 TH1 T2CON T2MOD RCAP2L RCAP2H TL2 TH2
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
QQQQ QQQ
QQQ
QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ
1. All SFRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
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Advance Information TABLE 3-4: UART SFRs References
Bit Access Type Register Name PCON SADDR SADEN SBUF SCON Address 87H A9H B9H 99H 98H Reference Section 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 7 6 5 4 3 2 1 0 Reset Value1 00x2x30000b 00H 00H xxH 00H Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
T3-4.0 1320
QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ
1. All SFRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2). 2. Bit 5 of PCON register (Brown-Out Flag) is cleared by Power-On reset, and it is not affected by other reset events. 3. Bit 4 of PCON register (Power-On Flag) is set by Power-On reset, and it is not affected by other reset events.
TABLE
3-5: SPI SFRs References
Bit Access Type Address D5H AAH 86H Reference Section 12.4.1 12.4.2 12.4.3 7 Q 6 5 4 3 2 1 0 Reset Value1 0x000100b 00xxxxxxb 00H Key Q: Read and Write -: Reserved Bit x: Indeterminate Value
T3-5.0 1320
Register Name SPCR SPSR SPDR
QQQQQQ
QQ
QQQQQQQQ
1. All SFRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
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3.5 Memory Mapped Configuration Registers (MMCR)
All Memory Mapped Configuration Registers are located in 8051 external data memory space, addresses 7F00H - 7FFFH. For the detailed description of MMCRs see the respective sections as specified Tables 3-6 through 3-25. Some of MMCRs contain reserved bits. On reads software 3.5.1 MMCR References TABLE 3-6: GPIO Input MMCRs References
Bit Access Type Register Name Address GPIOAIN GPIOBIN GPIOCIN GPIODIN GPIOEIN GPIOFIN GPIOGIN GPIOHIN GPIOIIN GPIOJIN GPIOKIN GPIOLIN GPIOMIN GPIONIN 7F1AH 7F1DH 7F20H 7F24H 7FA2H 7FA5H 7F3BH 7FE2H 7FE5H 7FE8H 7FEBH 7FA9H 7F6BH 7F84H Reference Section 9.1.2 9.1.6 9.1.11 9.1.15 9.1.18 9.1.22 9.1.26 9.1.30 9.1.34 9.1.39 9.1.44 9.1.48 9.1.51 9.1.55 7 6 5 4 3 2 1 0 Reset Value1 ppH ppH ppH ppH ppH ppH ppH ppH ppH ppH ppH ppH ppH ppH
T3-6.0 1320
must not rely on reserved bits being any particular value. On writes zeros should be written to reserved bits. When modifying a register with reserved bits the values read from the reserved bits can be written back to them. Software should not write to unused locations in MMCR space.
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit p: Pass through pin state
RRRRRRRR RRRRRRRR RRRRRRRR RRRRRRRR RRRRRRRR RRRRRRRR RRRRRRRR RRRRRRRR RRRRRRRR RRRRRRRR RRRRRRRR RRRRRRRR RRRRRRRR RRRRRRRR
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
(c)2006 Silicon Storage Technology, Inc.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 3-7: GPIO Output MMCRs References
Bit Access Type Register Name GPIOAOUT GPIOBOUT GPIOCOUT GPIODOUT GPIOEOUT GPIOFOUT GPIOGOUT GPIOHOUT GPIOIOUT GPIOJOUT GPIOKOUT GPIOLOUT GPIOMOUT GPIONOUT Address 7F19H 7F1CH 7F1FH 7F23H 7FA1H 7FA4H 7F3AH 7FE1H 7FE4H 7FE7H 7FEAH 7FA8H 7F30H 7F82H Reference Section 9.1.3 9.1.7 9.1.12 9.1.16 9.1.19 9.1.23 9.1.27 9.1.31 9.1.35 9.1.40 9.1.45 9.1.49 9.1.52 9.1.56 7 6 5 4 3 2 1 0 Reset Value1 FFH FFH FFH FFH FFH 11xxx111b FFH FFH FFH FFH FFH FFH FFH FFH
T3-7.0 1320
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQ QQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
TABLE
3-8: GPIO Direction MMCRs References
Bit Access Type Address 7F18H 7F1BH 7F1EH 7F22H 7FA3H 7F39H 7FE0H 7FE3H 7FE6H 7FE9H 7FA7H Reference Section 9.1.1 9.1.5 9.1.10 9.1.14 9.1.21 9.1.25 9.1.29 9.1.33 9.1.38 9.1.43 9.1.47 7 6 5 4 3 2 1 0 Reset Value1 00H 00H 0xxxxxxxb x0H 00xxx00xb 00H 00H 00H 00H 00H 00H
T3-8.0 1320
Register Name GPIOADIR GPIOBDIR GPIOCDIR GPIODDIR GPIOFDIR GPIOGDIR GPIOHDIR GPIOIDIR GPIOJDIR GPIOKDIR GPIOLDIR
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
QQQQQQQQ QQQQQQQQ Q QQQQ QQ
QQ
QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
33
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 3-9: GPIO Function Selection MMCRs References
Bit Access Type Register Name GPIOASEL GPIOBSEL GPIOCSEL GPIODSEL GPIOESEL GPIOFSEL GPIOGSEL GPIOHLOD GPIOISEL GPIOIOD GPIOJSEL GPIOJOD GPIOKPU GPIOMPU GPIOMOD GPIONPU GPIONOD Address 7F3DH 7F40H 7FDCH 7FDDH 7FDEH 7FA6H 7F3CH 7FABH 7FF0H 7FACH 7FF5H 7FADH 7FB7H 7F5BH 7FF6H 7F83H 7FFCH Reference Section 9.1.4 9.1.8 9.1.13 9.1.17 9.1.20 9.1.24 9.1.28 9.1.32 9.1.36 9.1.37 9.1.41 9.1.42 9.1.46 9.1.50 9.1.53 9.1.54 9.1.57 7 6 5 4 3 2 1 0 Reset Value1 00H 000000xxb x0000000b 00H C0H 000xxxx0b x0000000b 00H 0xH 00H 00H 00H xx000000b 00H 00H 00H 00H
T3-9.0 1320
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
QQQQQQQQ QQQQQQ QQQQQQQ
QQQQQQQQ QQQQQQQQ QQQ Q QQQQQQQ -
QQQQQQQQ QQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
34
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 3-10: GPIO Active Edge Selection MMCRs References
Bit Access Type Register Name GPIOESA GPIOESB GPIOESC GPIOESD GPIOESE GPIOESF GPIOESG GPIOESH GPIOESI GPIOESJ GPIOESK GPIOESL GPIOESM GPIOESN GPIOKINT GPIOESO GPIOESP GPIOESQ GPIOESR GPIOESS GPIOEST Address 7F57H 7F58H 7F5CH 7F5DH 7F60H 7F61H 7F62H 7F6CH 7F6DH 7F6EH 7F6FH 7FD0H 7FD1H 7FD2H 7FB8H 7FD3H 7FD4H 7FD5H 7FD6H 7FD7H 7FD8H Reference Section 8.3.19 8.3.22 8.3.25 8.3.28 8.3.31 8.3.34 8.3.37 8.3.40 8.3.43 8.3.44 8.3.47 8.3.48 8.3.51 8.3.52 8.3.53 8.3.56 8.3.57 8.3.60 8.3.61 8.3.64 8.3.65 7 6 5 4 3 2 1 0 Reset Value1 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H xx000000b 00H 00H 00H 00H 00H 00H
T3-10.0 1320
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
TABLE 3-11: Interrupt Source MMCRs References
Bit Access Type Register Name INTSRCA INTSRCAMSK INTSRCB INTSRCBMSK Address 7F00H 7F01H 7F02H 7F03H Reference Section 8.3.8 8.3.9 8.3.10 8.3.11 7 R R 6 R R 5 R R 4 R R 3 R 2 R R 1 Q R 0 R R Reset Value1 1000x000b 0000x000b 90H 00H Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
T3-11.0 1320
QQQQ
QQQ
QQQQQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
35
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 3-12: Wakeup Source MMCRs References
Bit Access Type Register Name WSRCA WSRCAMSK WSRCB WSRCBMSK KEYWSRC WSRCC WSRCCMSK WSRCD WSRCDMSK WSRCE WSRCEMSK WSRCF WSRCFMSK WSRCG WSRCGMSK WSRCH WSRCHMSK WSRCI WSRCIMSK WSRCJ WSRCJMSK WSRCK WSRCKMSK WSRCL WSRCLMSK WSRCM WSRCMMSK WSRCN WSRCNMSK WSRCO WSRCOMSK WSRCP WSRCPMSK Address 7F2AH 7F2BH 7F2CH 7F2DH 7F2FH 7F59H 7F5AH 7F5EH 7F5FH 7F63H 7F66H 7F64H 7F65H 7F55H 7F56H 7FAEH 7FAFH 7F3EH 7F3FH 7FC8H 7FC9H 7FCAH 7FCBH 7FCCH 7FCDH 7FCEH 7FCFH 7FB0H 7FB1H 7FDBH 7FECH 7FEDH 7FEEH Reference Section 8.3.12 8.3.13 8.3.14 8.3.15 8.3.16 8.3.17 8.3.18 8.3.20 8.3.21 8.3.23 8.3.24 8.3.26 8.3.27 8.3.29 8.3.30 8.3.32 8.3.33 8.3.35 8.3.36 8.3.38 8.3.39 8.3.41 8.3.42 8.3.45 8.3.46 8.3.49 8.3.50 8.3.54 8.3.55 8.3.58 8.3.59 8.3.62 8.3.63 7 6 5 4 3 2 1 R 0 Q Reset Value1 00000x10b 00000x00b 00xx0000b 00xx0000b xxxxxx00b 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H
T3-12.0 1320
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
QQQQQ QQQQQ R R QQ
QQ
QQQQ QQQQ QQ
QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
36
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 3-13: Timer MMCRs References
Bit Access Type Register Name WDTCSR WDTDAT HIBER Address 7F37H 7F38H 7FF3H Reference Section 10.4.1.1 10.4.1.2 10.5.1 7 Q 6 5 4 3 2 1 0 Reset Value1 0xxxxx00b FFH 00H Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
T3-13.0 1320
QQ
QQQQQQQQ QQQQQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
TABLE 3-14: PWM MMCRs References
Bit Access Type Register Name Address PWMPL0 PWMPL1 PWMPL2 PWMPH0 PWMPH1 PWMPH2 PWMC0 PWMC1 PWMC2 PWMD0 PWMD1 PWMD2 PWMCR PWM555CR1 7F25H 7F26H 7F29H 7F97H 7F98H 7F99H 7F9AH 7F9BH 7F9CH 7F9DH 7F9EH 7F9FH 7F96H 7F21H Reference Section 10.6.1.1 10.6.1.2 10.6.1.3 10.6.1.4 10.6.1.5 10.6.1.6 10.6.1.7 10.6.1.8 10.6.1.9 10.6.1.10 10.6.1.11 10.6.1.12 10.6.1.13 10.6.1.14 7 6 5 4 3 2 1 0 Reset Value1 FFH FFH FFH FFH FFH FFH FFH FFH FFH FFH FFH FFH 0000x000b x00p0000b
T3-14.0 1320
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value p: Pass through pin state
QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQ QQQ QQRQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
TABLE 3-15: SMBus MMCRs References
Bit Access Type Register Name Address SMCR0 SMCR1 SMSR0 SMSR1 SAR0 SAR1 SDSR0 SDSR1 SLSR SSCR 7F31H 7F67H 7F32H 7F68H 7F33H 7F69H 7F34H 7F6AH 7F88H 7F89H Reference Section 13.5.1 13.5.2 13.5.3 13.5.4 13.6.1 13.6.2 13.6.3 13.6.4 13.7.2 13.7.1 7 6 5 4 3 2 1 0 Reset Value1 00H 00H 00H 00H 0000000xb 0000000xb 00H 00H xxppppppb 00xxx001b
T3-15.0 1320
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value p: Pass through pin state
QQQQQQQQ QQQQQQQQ QQQQRRRR QQQQRRRR QQQQQQQ QQQQQQQ -
QQQQQQQQ QQQQQQQQ RRRRRR QQQ QQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
37
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 3-16: PS/2 MMCRs References
Bit Access Type Register Name Address PS2TX0 PS2TX1 PS2TX2 PS2RCV0 PS2RCV1 PS2RCV2 PS2CR0 PS2CR1 PS2CR2 PS2STS0 PS2STS1 PS2STS2 APS2STS0 APS2STS1 APS2STS2 PS2TMOUT PS2STATUS2 7F41H 7F45H 7F49H 7F41H 7F45H 7F49H 7F42H 7F46H 7F4AH 7F43H 7F47H 7F4BH 7FF7H 7FF8H 7FF9H 7F44H 7F48H Reference Section 14.4.1.1 14.4.1.2 14.4.1.3 14.4.2.1 14.4.2.2 14.4.2.3 14.4.3.1 14.4.3.2 14.4.3.3 14.4.4.1 14.4.4.2 14.4.4.3 14.4.4.4 14.4.4.5 14.4.4.6 14.4.5.1 14.4.5.2 7 6 5 4 3 2 1 0 Reset Value1 FFH FFH FFH 40H 40H 40H 50H 50H 50H 50H 50H 50H xxxx0000b 0000000xb
T3-16.0 1320
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
WWWWWWWW WWWWWWWW WWWWWWWW R R R Q Q Q R R R R R R R R R R Q Q Q R R R R R R R R R R Q Q Q R R R R R R R R R R Q Q Q R R R R R R R R R R Q Q Q R R R R R R Q R R R R Q Q Q R R R R R R Q R R R R Q Q Q R R R R R R Q R R R R Q Q Q R R R R R R Q -
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
TABLE 3-17: Fan Tachometer MMCRs References
Bit Access Type Register Name FANCNT1 FANCNT2 FAN1LD FAN2LD FANTIMEBASE Address 7FBAH 7FBBH 7FBCH 7FBDH 7FBEH Reference Section 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 7 R R 6 R R 5 R R 4 R R 3 R R 2 R R 1 R R 0 R R Reset Value1 00H 00H 00H 00H 00xx0101b Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
T3-17.0 1320
QQQQQQQQ QQQQQQQQ QQ QQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
TABLE 3-18: ADC MMCRs References
Bit Access Type Register Name ADDRA ADDRB ADDRC ADDRD ADDRL ADCSR Address 7F8EH 7F8FH 7F90H 7F91H 7F92H 7F93H Reference Section 16.2.1 16.2.2 16.2.3 16.2.4 16.2.5 16.2.6 7 R R R R R 6 R R R R R 5 R R R R R 4 R R R R R 3 R R R R R 2 R R R R R 1 R R R R R 0 R R R R R Reset Value1 00H 00H 00H 00H 00H 00H
T3-18.0 1320
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
QQQQQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 3-19: DAC MMCRs References
Bit Access Type Register Name DACDAT0 DACDAT1 DACDAT2 DACDAT3 DACCTRL Address 7F4CH 7F4DH 7F4EH 7F4FH 7F50H Reference Section 17.2.1 17.2.2 17.2.3 17.2.4 17.2.5 7 6 5 4 3 2 1 0 Reset Value1 00H 00H 00H 00H xxx00000b Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
T3-19.0 1320
QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
TABLE 3-20: KBC Host Interface MMCRs References
Bit Access Type Register Name KBCDATA KBCSTS AUXDATA KBDCFG PCOBF KEYSCAN Address 7FF1H 7FF2H 7FFAH 7FF4H 7FFDH 7F04H Reference Section 18.2.1 18.2.2 18.2.3 18.2.4 18.2.5 18.3.1 7 6 5 4 3 R 2 Q 1 R 0 R Q Reset Value1 00H 00H 00H 0x00x00xb xxxxxxx0b 20H
T3-20.0 1320
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
QQQQQQQQ QQQQ Q R QQ QQQQQQQQ QQ -
QQQQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
TABLE 3-21: GA20 Control MMCRs References
Bit Access Type Register Name GA20 SETGA20 RSTGA20 Address 7FFBH 7FFEH 7FFFH Reference Section 19.2.1 19.2.2 19.2.3 7 6 5 4 3 2 1 0 Q Reset Value1 xxxx00x1b 00H 00H Key Q: Read and Write -: Reserved Bit x: Indeterminate Value
T3-21.0 1320
QQ
QQQQQQQQ QQQQQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
TABLE 3-22: ACPI EC Interface MMCRs References
Bit Access Type Register Name ECIDATA ECIDATA1 ECISTS ECISTS1 ECICFG ECICFG1 Address 7F53H 7F80H 7F54H 7F81H 7F51H 7F52H Reference Section 20.2.1 20.2.2 20.2.3 20.2.4 20.3.1 20.3.2 7 6 5 4 3 2 1 0 Reset Value1 00H 00H 00H 00H xx000000b xx000000b
T3-22.0 1320
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
QQQQQQQQ QQQQQQQQ QQQQ QQQQ R R Q Q R R R R
QQQQQQ QQQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
39
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 3-23: MailBox MMCRs References
Bit Access Type Register Name MBX0 MBX1 MBX2 MBX3 MBX4 MBX5 MBX6 MBX7 MBX8 MBX9 MBXA MBXB MBXC MBXD MBXE MBXF MBX10 MBX11 MBX12 MBX13 MBX14 MBX15 MBX16 MBX17 MBX18 MBX19 MBX1A MBX1B MBX1C MBX1D MBX1E MBX1F MBX94 MBX96 MBX97 Address 7F08H 7F09H 7F0AH 7F0BH 7F0CH 7F0DH 7F0EH 7F0FH 7F10H 7F11H 7F12H 7F13H 7F14H 7F15H 7F16H 7F17H 7F70H 7F71H 7F72H 7F73H 7F74H 7F75H 7F76H 7F77H 7F78H 7F79H 7F7AH 7F7BH 7F7CH 7F7DH 7F7EH 7F7FH Reference Section 21.1.1 21.1.2 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.1.3 21.2.1 21.2.2 21.2.3 7 6 5 4 3 2 1 0 Reset Value1 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00x00xx0b xxxx0xxxb xxxx0xxxb
T3-23.0 1320
Key Q: Read and Write R: Read Only W: Write Only -: Reserved Bit x: Indeterminate Value
QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ R R Q R R Q Q -
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
40
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 3-24: Configuration MMCRs References
Bit Access Type Register Name Address LPCMON CFGINDEX CFGDATA 7F8AH 7F8CH 7F8DH Reference Section 23.1.1 23.1.2 23.1.3 7 6 5 4 3 2 1 0 Reset Value1 001xxx0pb 00H 00H Key Q: Read and Write R: Read Only -: Reserved Bit x: Indeterminate Value p: Pass through pin state
T3-24.0 1320
QQQ
QR
QQQQQQQQ QQQQQQQQ
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2).
TABLE 3-25: Miscellaneous MMCRs References
Bit Access Type Register Name MID DEVID DEVREV CLKSRCCON2 SRCROM2 RSTCON2 SFCS SFCMD SFAL SFAH SFAX SFDL SFDH SFSEC LPCSS PLLM2 PLLPS2 ALPCBC Address 7F05H 7F06H 7F07H 7F27H 7F28H 7F2EH 7FC0H 7FC1H 7FC2H 7FC3H 7FC6H 7FC4H 7FC5H 7FC7H 7FDFH 7F35H 7F36H 7F8BH Reference Section 3.5.2 3.5.3 3.5.4 5.3.2.1 4.4.1.1 5.2.3.1 4.4.5.1 4.4.5.2 4.4.5.3 4.4.5.4 4.4.5.5 4.4.5.6 4.4.5.7 4.7.1 9.1.9 5.3.2.2 5.3.2.3 4.8.2 7 R R R Q 6 R R R 5 R R R 4 R R R 3 R R R R 2 R R R 1 R R R 0 R R R R Reset Value1 BFH F0H 01H xx010100b x0H xxxxx001b 0xxx0x310b 00xx0000b 00H 00H 00H 00H 00H 0040000x30b xxxxx000b xx100010b xx110010b 0xxxxxxxb
T3-25.0 1320
Key Q: Read and Write R: Read Only -: Reserved Bit x: Indeterminate Value
QQ
QQ
QQQQ QQQ R Q QQ
QQ
QQQQ
QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ QQQQQQQQ Q QQQ QQQQQQ QQQQQQ -
1. All MMCRs returned to their reset values specified in the charts above after the following reset events: Power-On reset, External reset, Watchdog timer reset, Brown-out reset, 8051 firmware Soft reset, LPC Soft reset, and aLPC Soft reset (see also Section 5.2). 2. These selected MMCRs are also returned to their reset values after the following reset events: 8051 firmware Soft reset, and LPC Soft reset (see also Section 5.2). 3. Bit 2 of SFCS register and Bit 1 of the SFSEC register are affected by reset events as follows: After Power-On Reset, External reset, Watchdog timer reset, Brown-out reset, and aLPC Soft reset SFCS[2] = SFSEC[1] = 0 if ENVR location at address 0FFFH contains 0FFH value SFCS[2] = SFSEC[1] = 1 if ENVR location at address 0FFFH contains any value other than 0FFH After 8051 firmware Soft reset, and LPC Soft reset SFCS[2] is always cleared (`0'), and SFSEC[1] is preserved. These bits are not affected by other reset events. 4. Bit 6 of SFSEC register is reset only by Power-On reset, External reset, Brown-out reset, and LPC Interface reset.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 3.5.2 JEDEC Registers 3.5.2.1 JEDEC Manufacturer ID Register (MID)
Location 7F05H Read Write Reset 7 MID7 1 6 MID6 0 5 MID5 1 4 MID4 1 3 MID3 1 2 MID2 1 1 MID1 1 0 MID0 1
Symbol -
Function Not implemented, reserved for future use. Note: User should not write `1's to reserved bits. The value read from a reserved bit is indeterminate.
3.5.2.2 JEDEC Device ID Register (DEVID)
Location 7F06H Read Write Reset 7 ID7 1 6 ID6 1 5 ID5 1 4 ID4 1 3 ID3 0 2 ID2 0 1 ID1 0 0 ID0 0
Symbol -
Function Not implemented, reserved for future use. Note: User should not write `1's to reserved bits. The value read from a reserved bit is indeterminate.
3.5.2.3 Device Revision Register (DEVREV)
Location 7F07H Read Write Reset 7 REV7 6 REV6 5 REV5 4 REV4 Device Revision 3 REV3 Number1 2 REV2 1 REV1 0 REV0 -
1. Please contact SST to find out how this number corresponds to the SST79LF008 package markings.
Symbol -
Function Not implemented, reserved for future use. Note: User should not write `1's to reserved bits. The value read from a reserved bit is indeterminate.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
4.0 FLASH MEMORY PROGRAMMING 4.1 SuperFlash Memory Overview
The SST79LF008 flash memory is manufactured with SST's proprietary, high-performance SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain greater reliability and manufacturability compared with alternative technology approaches. The SuperFlash technology significantly improves the performance and reliability of the flash memory while lowering power consumption. The SST79LF008 allows flash Write operations (Program or Erase) in-system with a single 3.0-3.6V power supply, and it uses less energy during Erase and Program than alternative flash memory technologies for memory devices. The total energy consumed is a function of the applied voltage, current, and time of application. SuperFlash technology uses less current to program for any voltage range and has a shorter erase time than comparable technologies. This means that the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SuperFlash technology provides fixed Erase and Program times, independent of the number of the performed Erase/Program cycles. This eliminates the need to calibrate or correlate the system software or hardware to the cumulative number of erase cycles, which is necessary with alternative flash memory technologies whose Erase and Program times increase with accumulated Erase/Program cycles. To protect against inadvertent write, the SST79LF008 provides on-chip write protection. The SST79LF008 flash memory is offered with a typical endurance of 100,000 cycles and data retention of greater than 100 years. The SST79LF008 flash array is a (512K + 2K) x 16 sector erase, block erase, and word program embedded SuperFlash memory. It is organized as 512K words of Main Flash Memory array plus 2K words of erasable non-volatile registers (ENVR). In addition 1.5K words of user non-volatile registers (UNVR) can be one-time programmed. Key Features of SST79LF008 Flash Memory: * * * * * * * * * * SuperFlash Technology Organized as (512K Main array + 2K ENVR) x16 Single Voltage Read/Write Operations Endurance: 100,000 Cycles (typical) Greater than 100 years Data Retention Main array and ENVR write and read protection with a lock down/open after reset only option Uniform 2K Word sectors Uniform 32K Word blocks Sector-/Block-Erase Capability Fast Sector-/Block-Erase Time:
- 55 ms typical - 60 ms max * Fast Word-Program Time: - 15 s typical - 60 s max
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
4.2 Flash Memory Map
The map of SST79LF008 main flash memory array is shown in Figure 4-1. It includes a total 1 MByte (8 Mbit) flash memory space. A maximum of 128 KByte KBC firmware block can be located in the lower part of flash memory to store the 8051-specific keyboard and embedded controller code. The other flash memory area can be used to store the system BIOS related code and data. See Section 7.0 for the details on mapping SST79LF008 flash memory into the system LPC interface address space.
FFFFFH F0000H EFFFFH
Block 15 (64 KByte)
Blocks 14-2 (13 Blocks - 64 KByte each)
20000H 1FFFFH 10000H 0FFFFH 00000H
Block 1 (64 KByte) Block 0 (64 KByte)
1245 FlshMemMap.0
KBC Firmware in 17-bit addressing mode (ACON[1]=1) KBC Firmware in 16-bit addressing mode (ACON[1]=0)
FIGURE
4-1: SST79LF008 Flash Memory Map 4.2.2 Programming Modes The SST79LF008 internal flash memory (including ENVR and UNVR spaces) can be programmed through a Shared ROM Interface using the following three methods: * * * In-Application Programming Mode (8051 controlled) Remote aLPC Programming Mode (aLPC Host controlled) In-system LPC Programming Mode (LPC Host controlled)
4.2.1 ENVR / UNVR Address Space The maps of ENVR and UNVR address spaces are shown in tables below. TABLE
Address FFFH 000H-FFEH
4-1: ENVR Address Space
Contents EnableBoot Byte (see Section 4.5) Erasable NVR for user
T4-1.0 1320
TABLE
Address
4-2: UNVR Address Space
Contents 3K OTP for User NVR
T4-2.0 1320
The first two modes are described in this section. For LPC programming mode, see Section 7.0.
000H-BFFH
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
4.3 Shared ROM Interface
The SST79LF008 Shared ROM Interface (SRI) provides LPC Host, alternate LPC (aLPC) Host and the 8051 MCU with access to the entire 1 MByte of main Flash memory array as well as to ENVR and UNVR areas. See Figure 4-2. until the LPC Host sends a Release LPC Soft Reset command, which re-starts 8051 code execution. As KBC operation is aborted and then restarted, this mechanism is not recommended for LPC Host program/erase access, unless flash memory is blank or corrupted.
LPC Bus Host Interface
Shared-ROM Interface
8051 Core
Flash Memory
1245 ShrdROM.0
FIGURE
4-2: Shared ROM Interface
Both LPC and aLPC Hosts access flash memory via the internal LPC bus interface unit (see details on switching bus control between LPC Host and aLPC Host in Section 4.8). The aLPC Host flash access is exclusive as 8051 is forced into reset state while aLPC mode is enabled. The LPC Host and 8051 may access flash memory concurrently. For LPC Host read operations the arbitration between LPC Host and 8051 is completely handled by SRI hardware. For LPC Host program/erase operation flash memory access arbitration must be implemented in software via one of the following mechanisms: 1. 8051 firmware turns over the flash bus to the LPC Host by setting HOST_ACCESS bit in SFCS register, see Section 4.4.5, In this case 8051 firmware must run from the Scratch ROM, described in Section 4.4.1, just before and while the flash bus is released to the LPC Host. 2. 8051 firmware enters Idle mode, which allows the LPC Host software to take over the flash bus by setting the STP_CLK bit in MBX94 register, described in Section 21.2. In this case 8051 firmware can run from flash before entering Idle mode provided the LPC Host does not update the respective flash locations. For any mechanism above, the LPC Host software can confirm the bus turn around by checking the HOSTFLASH bit in MBX94 register. See Section 21.2. 3. 8051 firmware enables LPC Soft reset via LPCMON register, detailed in Section 23.1, which allows the LPC Host to take over the flash bus by sending a Force LPC Soft Reset command, detailed in Section 7.3. In this case 8051 will be kept in reset state and 8051 firmware will not run
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Advance Information
4.4 In-Application Programming Mode
During In-Application programming (IAP), the 8051 executes instructions from the scratch ROM, which is a portion of XRAM mapped to the top or bottom of the first 64 KByte (Block0) in the 8051 program space. The flash control registers SFCS, SFCMD, SFAL, SFAH, SFDL, and SFDH located among the memory-mapped registers, control and monitor the device's erase and program operations. 4.4.1 Scratch ROM Mapping Control The IAP code must be executed from 8051 program memory space that is not on the flash. For this purpose the SST79LF008 allows a section of on-chip XRAM to be mapped to 8051 program space. The memory-mapped register SCRROM, described below, controls the mapping of XRAM to 8051 program address space. Mapping can affect the entire 2K expanded RAM, or only part of it, as indicated by SCRSIZE field. Table 4.3 details scratch ROM mapping to 8051 program space. See also Figures 3-2 to 3-6.
4.4.1.1 Scratch ROM Control Register (SCRROM)
Location 7F28H Read/Write Reset 7 X 6 X 5 X 4 X 3
SCRSIZE1
2
SCRSIZE0
1 SCRPOS 0
0 SCREN 0
0
0
Symbol
Function Not implemented, reserved for future use. Note: User should not write `1's to reserved bits. The value read from a reserved bit is indeterminate. Not defined Scratch ROM size 00: 256 Bytes 01: 512 Bytes 10: 1024 Bytes 11: 2048 Bytes Scratch ROM position 1: Map to Block0 top 0: Map to Block0 bottom Scratch ROM mapping enable 1: Enable mapping 0: Disable mapping
X SCRSIZE[1:0]
SCRPOS
SCREN
TABLE
SCREN 0 1 1 1 1 1 1 1 1
4-3: Scratch ROM Mapping
SCRPOS X 0 0 0 0 1 1 1 1 SCRSIZE[1:0] XX 00 01 10 11 00 01 10 11 XRAM Section Address 000H - 7FFH 700H - 7FFH 600H - 7FFH 400H - 7FFH 000H - 7FFH 700H - 07FFH 600H - 7FFH 400H - 7FFH 000H - 7FFH Program Space Address No Mapping 0000H - 00FFH 0000H - 01FFH 0000H - 03FFH 0000H - 07FFH FF00H - FFFFH FE00H - FFFFH FC00H - FFFFH F800H - FFFFH
T4-3.0 1320
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 4.4.2 IAP Mode Control The IAP enable bit, SFCS[7], enables in-application programming mode. Until this bit is set, all flash programming IAP commands will be ignored. Table 4-4 contains the In-Application Programming commands that can be used when IAP mode is enabled. All IAP commands should be executed from the Scratch ROM by writing the command code to SFCMD register after TABLE
Operation Reserved2 Sector-Erase Block-Erase Word- Program Erase-Suspend Erase-Resume Word-Read No Operation
address and data registers are properly loaded, see Figures 4-3 to 4-6. The command codes not listed in the table are reserved. The same commands are used to access either main 1MByte flash array, or 4 KByte flash ENVR, or 3 KByte OTP UNVR. The selection of the target memory area is controlled by bits SFCMD[7:6].
4-4: IAP Commands1 for SST79LF008
SFCMD[3:0] 0000b, 1110b 0001b 0010b 0011b 0100b 0101b 1111b Remaining Combinations SFDH[7:0] X3 X X DH6 X X DH6 X3 SFDL[7:0] X X X DL6 X X DL6 X SFAX[7:0] X AX4 AX4 AX4 X X AX4 X SFAH[7:0] X AH5 AH5 AH5 X X AH5 X SFAL[7:0] X X X AL7 X X AL7 X
T4-4.0 1320
1. 2. 3. 4. 5. 6. 7.
SFCS[7] = 1 enables IAP commands; SFCS[7] = 0 disables IAP commands. Do not use reserved values. X = "Don't care" AX = Word Address most significant order byte (SFAX[7:3] = 0, SFAX[2:0] = Word address bits 18:16). AH = Word Address high order byte (SFAH[7:0] = Word address bits 15:8). DH = Data high byte (input or output); DL = Data low byte (input or output). AL = Word Address low order byte (SFAL[7:0] = Word address bits 7:0).
4.4.3 Address Selection for IAP Commands Only word access is supported in IAP mode. Three address registers (SFAX, SFAH and SFAL) are provided to specify 24-bit word address for any individual word location. Only 19 bits of these registers are significant for access to 512 KWord main flash array, bits 23:19 (SFAX[7:3]) must be always 0. Sixteen 32 KWord blocks in the main flash array can be erased independently. There are 16 sectors of 2 KWord in each block, and each sector can also be erased independently. In addition the 2 KWord ENVR flash sector can be erased in IAP mode. For block or sector selection SFAX, SFAH, and SFAL registers should be loaded with any valid word address within the respective block or sector.
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Advance Information 4.4.4 IAP Mode Commands Description 4.4.4.1 No Operation The No Operation command causes the flash controller to do nothing. 4.4.4.2 Sector-Erase The Sector-Erase command erases all bytes in a sector. The sector size is 2 KWord (4 KByte). The selection of the sector to be erased is determined by the contents of SFAX and SFAH registers. For example, to erase sector FF000HFFFFFH of the main flash array the following settings should be used. 4.4.4.3 Block-Erase The Block-Erase command erases all bytes in a 32 KWord (64 KByte) memory block. The selection of the block to be erased is determined by the contents of SFAX and SFAH registers. For example, to erase block F0000H-FFFFFH of the main flash array the following settings should be used.
IAP Enable ORL SFCS, #80H
IAP Enable ORL SFCS, #80H
Configure block address MOV SFAX, #07H MOV SFAH, #80H
Configure sector address MOV SFAX, #007H MOV SFAH, #0F8H
Block-Erase Command MOV SFCMD, #02H
SFCF[1]=1b indicates operation completion
1245 BlockErs.0
Sector-Erase Command MOV SFCMD, #01H
FIGURE
4-4: IAP Block-Erase
SFCF[1]=1b indicates operation completion
1245 SectorErs.0
FIGURE
4-3: IAP Sector-Erase
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 4.4.4.4 Word-Program The Word-Program command programs data into a single word location in the flash memory. The word address is determined by the contents of SFAX, SFAH and SFAL registers. The data to be programmed is stored in registers SFDH (high byte) and SFDL (low byte). For example, to program word data to the main flash array at word address 7F801H (which results in storing high byte word data at byte address FF003H, and low byte word data at byte address FF002H) the following settings should be used. 4.4.4.6 Erase-Resume The Erase-Resume command resumes the erase process in the suspended sector or block. After the Erase-Resume command is issued, the device will resume the erase process. Erase cannot be resumed until the Word-Read or Word-Program operation already in progress has been completed. 4.4.4.7 Word-Read The Word-Read command allows the user to verify that the device has correctly performed an Erase or Program command. Word-Read returns the data word in registers SFDH (high byte) and SFDL (low byte) if the command is successful. The user must check if the previous flash operation has been fully completed before issuing a Word-Read. Word-Read command execution time is short enough that there is no need to poll for command completion. The address is determined by the contents of SFAX, SFAH and SFAL registers. For example, to read word FF003H:FF002H of the main flash array the following settings should be used.
IAP Enable ORL SFCS, #80H Configure word address MOV SFAX, #007H MOV SFAH, #0F8H MOV SFAL, #001H
Configure Data to SFDH, SFDL MOV SFDH, #word_dataH MOV SFDL, #word_dataL
Word-Program Command MOV SFCMD, #03H SFCF[1]=1b indicates operation completion
1245 WordPgm.0
IAP Enable ORL SFCS, #80H Configure word address MOV SFAX, #007H MOV SFAH, #0F8H MOV SFAL, #001H
FIGURE
4-5: IAP Word-Program
Word-Read Command MOV SFCMD, #0FH SFDH = Data (FF003H) SFDL = Data (FF002H)
1245 WordRead.0
4.4.4.5 Erase-Suspend The Erase-Suspend command allows a Sector-Erase or Block-Erase operation interruption in order to read or program data into another block of memory. Once the EraseSuspend command is executed, the device will suspend the on-going erase operation. After a successful Erase-Suspend, a Word-Read or WordProgram command can be issued to read from or write to a different sector/block of flash memory than the one suspended. If a Word-Read command is issued to an address within the suspended sector or block, the read operation may return invalid data. If a Word-Program command is issued to an address within the suspended memory area, the command is acknowledged but rejected. Suspended operations cannot be nested. That is, the system needs to complete/resume any previously suspended operation before a new operation can be suspended.
FIGURE
4-6: IAP Word-Read
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 4.4.5 SuperFlash Control and Status Registers 4.4.5.1 SuperFlash Control and Status Register (SFCS)
Location 7FC0H Read Write Reset 0 X X X 0 X 7
IAPEN
6
-
5
-
4
-
3
SOFTRST
2
OVERLAY
1
FLASH_RDY
0
HOST_ACCESS
1 0
Symbol
Function Not implemented, reserved for future use. Note: User should not write `1's to reserved bits. The value read from a reserved bit is indeterminate. Not defined 8051 controlled IAP mode Enable bit 1: Enable IAP mode 0: Disable IAP mode This bit can be set by the 8051 firmware only while it is running from the Scratch ROM. The firmware must not restart running from flash until this bit is cleared. 8051 controlled Soft Reset A transition of this bit from 0 to 1 will generate an 8051 soft reset (see Section 5.2 for the effect of this reset event) BootRom Overlay bit 1: BootRom (0F000H? 0FFFFH) is mapped to bottom 4 KByte sector in 8051 program space (00000H - 00FFFH), 0: BootRom (0F000H - 0FFFFH) is NOT mapped to bottom 4 KByte sector in 8051 program space The reset value of this bit is determined as follows. 1. After Power On Reset, External pin reset, Watchdog timer reset, Brownout reset OVERLAY = 0 if the ENVR location at address 0FFFH contains 0FFH value. OVERLAY = 1 if the ENVR location at address 0FFFH contains any value other than 0FFH 2. After 8051 soft reset, LPC soft reset, and aLPC soft reset, OVERLAY = 0 always. 3. Once the byte at location 0FFFH of ENVR is programmed, it can only be restored by ENVR erase, but software can always change the value of OVERLAY bit at run time without the need of ENVR erase. OVERLAY bit affects only flash memory access addressed via 8051 program counter (PC). It does not affect physical addresses used in IAP mode for flash memory programming commands.
X IAPEN
SOFTRST
OVERLAY
FLASH_RDY
Indicates program or erase completion in IAP mode. 1: Ready - IAP command is completed 0: Busy - IAP command is in progress Flash bus ownership control bit. 1: 8051 released flash bus to LPC Host 0: 8051 owns the flash bus
HOST_ACCESS
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 4.4.5.2 SuperFlash Command Register (SFCMD)
Location 7FC1H Read/ Write Reset 7 UNVRSEL 0 6 ENVRSEL 0 5 X 4 X 3 FCM3 0 2 FCM2 0 1 FCM1 0 0 FCM0 0
Symbol
Function Not implemented, reserved for future use. Note: User should not write `1's to reserved bits. The value read from a reserved bit is indeterminate. Not defined Select UNVR as target for IAP command. Select ENVR as target for IAP command.
SFCMD[7:6] 1X 01 00 Operation Select UNVR1 Select ENVR2 Select Main flash array
X UNVRSEL ENVRSEL
1. Valid address for 3 KB UNVR area is from 0000H to 0BFFH 2. Valid address for 4 KB ENVR area is from 0000H to 0FFFH
FCM[3:0]
IAP mode flash command
SFCMD[3:0] 0000 0001 0010 0011 0100 0101 1111 Operation No Operation Sector-Erase Block-Erase Word-Program Erase-Suspend Erase-Resume Word-Read
Note:All commands should be issued from the Scratch ROM while 8051 owns the flash bus. The SFCMD[3:0] bits are automatically cleared by hardware during command execution, and read back operation returns 0 in FCM field. If command is issued while LPC Host owns the flash bus, it will be ignored and read back operation returns previously written command in FCM field.
4.4.5.3 SuperFlash Address Register (SFAL)
Location 7FC2H Read/ Write Reset 7 SFAL7 0 6 5 4 3 SFAL3 0 2 1 0
SFAL6
0
SFAL5
0
SFAL4
0
SFAL2
0
SFAL1
0
SFAL0
0
Symbol SFAL[7:0]
Function Flash Word Address low order byte.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 4.4.5.4 SuperFlash Address Register (SFAH)
Location 7FC3H Read/ Write Reset 7 SFAH7 0 6 5 4 3 SFAH3 0 2 1 0
SFAH6
0
SFAH5
0
SFAH4
0
SFAH2
0
SFAH1
0
SFAH0
0
Symbol SFAH[7:0]
Function Flash Word Address high order byte.
4.4.5.5 SuperFlash Address Register (SFAX)
Location 7FC6H Read/ Write Reset 7 SFAX7 0 6 5 4 3 SFAX3 0 2 1 0
SFAX6
0
SFAX5
0
SFAX4
0
SFAX2
0
SFAX1
0
SFAX0
0
Symbol SFAX[7:0]
Function Flash Word Address most significant order byte.
Note:SFAX, SFAH and SFAL registers are cascaded to form a linear Word Address of the entire 8 Mbit on-chip flash memory (Word Address = (Byte Address)/2).
4.4.5.6 SuperFlash Data Low Register (SFDL)
Location 7FC4H Read/ Write Reset 7 SFDL7 0 6 5 4 3 SFDL3 0 2 1 0
SFDL6
0
SFDL5
0
SFDL4
0
SFDL2
0
SFDL1
0
SFDL0
0
Symbol SFDL[7:0]
Function Flash data low byte. For read flash command reading this register returns the low byte of word data from the flash. For write flash command SFDL contains the low byte of word data to be programmed. (SST79LF008 only supports word-wide access in IAP mode).
4.4.5.7 SuperFlash Data High Register (SFDH)
Location 7FC5H Read/ Write Reset 7 SFDH7 0 6 5 4 3 SFDH3 0 2 1 0
SFDH6
0
SFDH5
0
SFDH4
0
SFDH2
0
SFDH1
0
SFDH0
0
Symbol SFDH[7:0]
Function Flash data high byte. For read flash command reading this register returns the high byte of word data from the flash. For write flash command SFDH contain the high byte of word data to be programmed. (SST79LF008 only supports word-wide access in IAP mode).
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Advance Information
4.5 BootRom Area
BootRom area physically occupies top 4KByte of flash memory Block0 at addresses from 0F000H to 0FFFFH. Bit 2 OVERLAY of the SFCS register controls logical mapping of the BootRom area. When OVERLAY = 1, BootRom is enabled to overlay the bottom 4 KByte address of flash memory. The overlay mode only affects the memory access addressed via 8051 program counter (PC). It does not affect the physical addresses of flash memory locations used for memory access by flash programming commands. When OVERLAY = 0, BootRom overlay mode is disabled. The OVERLAY bit can be altered at run-time and any change takes effect immediately. Hence, it is recommended that the OVERLAY bit be changed by the code outside the overlapped bottom 4 KByte address range. TABLE 4-5: OVERLAY Bit Value After RESET
OVERLAY (SFCS[2]) 0 Description No overlay. After reset 8051 starts execution at physical address 0000H. Overlay. 0F000H to 0FFFFH (top 4KB of 64KB) overlays to 0000H to 0FFFH (bottom 4KB of 64KB). After reset 8051 starts execution from BootRom at physical address 0F000H.
T4-5.0 1320
The Power-on reset, Brown-out reset, External pin reset, and Watchdog timer reset will set/clear OVERLAY bit according to the EnableBoot byte in ENVR as shown in Table 4-5. 8051 soft reset (via SFCS.3 bit), LPC and aLPC soft resets clear OVERLAY bit regardless of ENVR state and re-start KBC firmware always from 0000H physical address. EnableBoot is a non-volatile flash byte, and it is located at address 0FFFH (last byte) of ENVR. After ENVR is erased, the default value is 0FFH. This non-volatile byte can be programmed by IAP command, or via LPC, or aLPC bus. Since SST79LF008 only supports word program, in order to program EnableBoot byte, the entire word 0FFFH:0FFEH has to be updated.
EnableBoot Byte (ENVR Address 0FFFH) 0FFH (Default Value) (BootRom Disabled) Non-0FFH (BootRom Enabled)
1
4.6 LPC Flash Programming Mode
The SST79LF008 flash memory array can be programmed independently by the LPC Host through the LPC bus interface. See Section 7.0 for the detailed description of all LPC Flash commands.
4.7 8051 Controlled Security
SST79LF008 provides an 8051 controlled read/write lock protection through a SuperFlash Security Control Register (SFSEC) in Section 4.71.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 4.7.1 SuperFlash Security Control Register (SFSEC)
Location 7FC7H Read/ Write Reset 7 BTLK 0 6 STICKY_ LK 0 5 W_LOCK 0 4 R_LOCK 0 3 W_LOCK_ KBC 0 2 NO_MAP_ KBC 0 1 W_LOCK_ BTROM X 0 NO_MAP_ BTROM 0
Symbol X BTLK
Function Not defined 8051 Boot sector lock bit (valid for 8051 IAP and LPC Flash programming modes) 1: Lock - 4 KByte sector at physical address 0000H - 0FFFH is write-protected 0: No Lock ENVR sector lock bit (valid for 8051 IAP and LPC Flash programming modes). This bit can be set by 8051 firmware but it is cleared only by the following hardware reset events: Power On reset, Brown out reset, External pin reset, and LPC Reset. 1: Lock - ENVR is read-protected and write-protected (read returns 00H) 0: No Lock BIOS flash write lock bit (valid for LPC Flash programming mode only) 1: Lock - BIOS flash memory area is write-protected (BIOS flash area is Block2Block15 = 7.0 Mbit, or Block1-Block15 = 7.5 Mbit depending on the status of ACON[1] bit. See Section 6.5) 0: No Lock BIOS flash read lock bit (valid for LPC Flash programming mode only) 1: Lock - BIOS flash memory area is read-protected (BIOS flash area is Block2Block15 = 7.0 Mbit, or Block1-Block15 = 7.5 Mbit depending on the status of ACON[1] bit. See Section 6.5; LPC read access to BIOS area returns 00H). 0: No Lock KBC flash write lock bit (valid for 8051 IAP and LPC Flash programming modes). 1: Lock - KBC flash memory area is write-protected (KBC flash area is Block0Block1 = 128 KByte, or Block0 = 64 KByte depending on the status of ACON[1] bit. See Section 6.5) 0: No Lock KBC flash mapping control bit 1: KBC area is hidden from the LPC host (KBC flash area is Block0-Block1 = 128 KByte, or Block0 = 64 KByte depending on the status of ACON[1] bit. See Section 6.5; LPC read access to KBC area returns 00H). 0: KBC area is visible to LPC host. Write lock for BootRom area (valid for 8051 IAP and LPC programming modes). 1: Lock - BootRom area at physical address 0F000H - 0FFFFH is write-protected. 0: No Lock The reset value of this bit is determined as follows. After Power On Reset, External pin reset, Watchdog timer reset, Brown out reset W_LOCK_BTROM = 0 if the ENVR location at address 0FFFH contains 0FFH W_LOCK_BTROM = 1 if the ENVR location at address 0FFFH contains any value other than 0FFH BootRom mapping control bit. 1: BootRom area at physical address 0F000H - 0FFFFH is hidden from the LPC host (LPC read access to BootRom area returns 00H). 0: BootRom area is visible to LPC host.
STICKY_LK
W_LOCK
R_LOCK
W_LOCK_KBC
NO_MAP_KBC
W_LOCK_BTROM
NO_MAP_BTROM
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information There are two sets of lock and mapping control bits that provide read, and write (program/erase) protection on a per-block basis. The first set is controlled by 8051 core, which can protect the BIOS memory space through the W_LOCK and R_LOCK bits, and KBC firmware space through W_LOCK_KBC, NO_MAP_KBC, BTLK, W_LOCK_BTROM, and NO_MAP_BTROM bits. The second set is controlled by the LPC host, which can set read or write protections of the flash blocks through block locking registers T_MINUS18_LK, ..., T_BLOCK_LK described in Section 7.0. The LPC host also controls mapping of KBC firmware area via Bit 4 of Mailbox register 94 described in Section 21.0. Only the protection status set by the 8051 core applies to 8051 firmware initiated Read or Write operations. For LPC host initiated Read or Write operations, both sets of the protection and mapping attributes take effect and the more restrictive one applies. All of the above locks do not apply to aLPC programming mode.
HW Snooper
aLPC Bus
LPC Bus
aLPC (3 pins)
LPC Pins (6 pins)
GPI Alternate Functions
LPC BIU
1245 aLPC-logic.0
4.8 aLPC MODE
4.8.1 Alternate LPC (aLPC) Interface Besides the standard LPC bus, the SST79LF008 implements an alternate LPC (aLPC) bus to support remote insystem-programming of the on-chip Flash. Either the LPC bus or the aLPC bus may be connected to the internal LPC bus interface unit (BIU) as shown on Figure 4-7. TABLE 4-6: aLPC Snooper Command Sequences
1st Bus Write Cycle1 Command Sequence aLPC Mode Enable_and_Poll aLPC Mode Switch_and_Reset aLPC Mode Exit Addr 55H 55H 55H Data AAH AAH C5H
FIGURE
4-7: aLPC Logic Diagram
A 3-wire input hardware snooper circuit is used to switch the 3 aLPC signals (aLFRAME#, aLCLK and aLAD) from their default GPI mode to aLPC bus mode, upon detecting a unique non-random pattern stream of the "Enable_and_Poll" sequence described in Table 4-6.
2nd Bus Write Cycle1 Addr AAH AAH AAH Data 55H 55H B6H
3rd Bus Write Cycle1 Addr 55H 55H Data B7H B7H
4th Bus Write Cycle1 Addr AAH AAH Data AFH 52H
T4-6.0 1320
1. Each Write Cycle is an aLPC I/O Write Cycle (See Section 4.8.6)
There are 3 states of the aLPC Snooper: IDLE, READY and SWITCHED to aLPC mode. After Power-on, Brownout, External pin, and WDT resets, the SST79LF008 Snooper will start from IDLE state. In IDLE state LPC bus is connected to the internal LPC interface unit, and hardware only snoops for Enable_and_Poll aLPC sequence, no other sequence will get the Snooper out of IDLE state. After successfully
receiving a full Enable_and_Poll command, an interrupt is sent to the 8051 and the hardware Snooper will go to READY state. In READY state, the hardware snoops for all command sequences: * If the hardware snoops an aLPC Exit_and_Reset sequence, it will go to IDLE state.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information * If the hardware snoops an Enable_and_Poll sequence, it will stay in READY state and return the status of RDY4ALPC bit on aLFRAME# line during SYNC phase of the fourth write cycle of the Enable_and_Poll sequence. (If the RDY4ALPC bit in the ALPCBC register is set, the Snooper will drive aLFRAME# low during SYNC phase, otherwise the Snooper will not drive aLFRAME# at all.) No interrupt to the 8051 is generated by the Snooper in the READY state. If hardware snoops a Switch_and_Reset sequence, it will proceed to SWITCHED state, which enable aLPC flash programming mode.
Exit_and_Reset
All aLPC Snooper command sequences utilize aLPC I/O Write cycles described in Section 4.8.5. The following figure illustrates the relationship between three states of the aLPC snooper.
Reset
(POR, BOR, External, WDT)
IDLE
~Enable_and_Poll
*
Enable_and_Poll
The aLPC Host can issue Switch_and_Reset sequence immediately after Enable_and_Poll to force the aLPC mode entry, or it can poll RDY4ALPC bit to make sure that 8051 is ready to switch. The former scenario is recommended when programming a blank chip, or if 8051 firmware is corrupted; the latter scenario provides handshaking with 8051 firmware for graceful entry to the aLPC mode. In SWITCHED state (aLPC mode) 8051 is permanently kept in rest condition and aLPC bus is connected to internal LPC interface unit. Hardware only snoops for aLPC Exit_and_Reset sequence, which returns Snooper back to IDLE state. In SWITCHED state aLPC flash commands described in Section 4.8.6 are used to access the entire SST79LF008 flash memory. aLPC Bus Control Register (ALPCBC)
Location 7F8BH Read/ Write Reset 7 RDY4ALPC 0 6 X 5 X 4 X
READY
~(Exit_and_Reset || Switch_and_Reset)
Switch_and_Reset
Exit_and_Reset
SWITCHED
~Exit_and_Reset
1245 aLPC-snpr.0
FIGURE
4-8: aLPC Snooper State Machine
3 X
2 X
1 X
0 X
Symbol X RDY4ALPC
Function Not implemented Not defined 8051 is ready for entering aLPC mode. While the Snooper is in IDLE or READY state 8051 can write to this bit. On entry into the SWITCHED state (aLPC mode) this bit is cleared by hardware. 1: 8051 is ready for aLPC mode. 0: 8051 is not ready for aLPC mode.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 4.8.2 aLPC Access to BIOS and KBC Code After entering SWITCHED state a downloader or hardware dongle which functions as an aLPC Host has access to the entire SST79LF008 Flash Memory including ENVR and UNVR. Both BIOS and KBC code can be programmed via the aLPC interface pins using aLPC Memory Write/Read TABLE
Symbol aLCLK aLAD
cycles described in Sections 4.8.4 and 4.8.5, with aLPC flash commands listed in Section 4.8.6. For aLPC pin descriptions, see Table 4-7. All flash memory protection mechanisms (block locking and mapping control) are disabled in aLPC mode.
4-7: aLPC Pin Descriptions
Pin Name Clock Address and Data Type I I/O Functions To provide a clock input to the control unit (Host driven always) To provide aLPC bus information such as addresses, commands, and data (Host or device driven depending on the direction of the transfer.1) To indicate the start of an aLPC cycle (external aLPC Host driven), and the Ready or Busy status of the device (SST79LF008 driven2). Also used by the Host to abort an aLPC cycle in progress.
T4-7.0 1320
aLFRAME#
Frame
I/O
1. External pull-up resistor should be connected to the aLAD pin in order to maintain pin state during turn-around cycles. 2. The aLFRAME# signal is driven low to indicate Busy, and tri-stated to indicate Ready status. Hence, the external pull-up resistor should also be connected to the aLFRAME# pin.
4.8.3 aLPC Memory Write Operation with AutoAddress Increment and Multi-Byte Programming The aLPC Mode with Auto-Address Increment (AAI) and Multi-Byte Programming features are provided for highspeed programming through the aLPC Host. The AutoAddress Increment in aLPC mode allows loading for only one address for each group of 1, 2, 4, 16, 128-byte, 4K, 64K, or 1M-byte of data. The Multi-Byte Programming feature supports multi-byte programming within one aLPC cycle. All aLPC flash commands listed in Section 4.8.6 utilize aLPC Memory Write cycles described in this section. In aLPC mode aLAD is the only Data/Address input available, hence aLPC Memory Write cycles are similar to the standard LPC Firmware Memory Write cycles with the exception of using 4 clocks (instead of 1) to transfer each field as shown in Table 4-8-3. The aLPC interface also provides an extended handshaking mechanism between the aLPC Host and the ST79LF008 device for write cycles using the aLFRAME# pin. When the aLPC Host starts a write cycle, the Host drives aLFRAME# low until the START field is transferred. Then the Host drives aLFRAME# high for four cycles. After
those, the Host floats aLFRAME# and monitors the aLFRAME# signal, which is controlled by the SST79LF008 device in order to output Ready/Busy status. The SST79LF008 device would drive aLFRAME# low when the write-buffer is full or the flash memory is busy. When the SST79LF008 device is ready to receive data from the Host, aLFRAME# is switched to high. Data in the aLPC Data Field is accepted until the internal buffer is full. At that point the device asserts the aLFRAME# low (busy) at the falling edge of aLCLK for the most significant bit of the last accepted nibble to indicate that the internal buffer is full and cannot accept any more data. The clock aLCLK must not be stopped during the program/erase procedure but any data present on aLAD line will be ignored while aLFRAME# is low. When the device is ready, the aLFRAME# signal is deasserted at the falling edge of aLCLK to indicate to the Host that more data (the next group of bytes/bits) can be accepted by the internal data buffer. At this point the host should generate 4 additional aLCLK clock pulses before sending any more data. See Figure 4-9 for example of aLPC Memory Write cycle including handshaking operations.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE
Clock Cycle 0-3
4-8: aLPC Memory Write Cycle Field Definitions
Field Name START Field Contents 0,1,1,1
SST79LF008
aLAD IN1
Comments aLFRAME# must be active (low) for the part to respond. Only the last four clocks of the start field (before aLFRAME# transitioning high) should be recognized. The START field contents indicate aLPC Firmware Memory Write cycle (value = 1110). Order of bit transfer for this field: LS Bit first ID selects SST79LF0008 device to respond. If the IDSEL field matches the device ID, then that particular device will respond to the whole bus cycle. Valid IDs = 0000 or 0001. Order of bit transfer for this field: LS Bit first These 28 clock cycles make up the 28-bit starting memory address A27-A0. Order of bit transfer for this field: MS Nibble first, LS Bit first: A24,A25,A26,A27, A20,A21,A22,A23, A16,A17,A18,A19, A12,A13,A14,A15, A8,A9,A10,A11, A4,A5,A6,A7, A0,A1,A2,A3 Device will execute multi-byte write for N bytes. Valid field values S = 0, 1, 2, 4, 7, 12, 13, 14 For the respective N = 1, 2, 4, 16, 128, 4K, 64K, 1M bytes Order of bit transfer for this field: LS Bit first Data field consists of 8*N clock periods, where N is defined by MSIZE field. The host will insert wait cycles and pause the data stream when aLFRAME# goes low until it returns high, signifying that the chip is ready for more data. Order of bit transfer for this field: LS Nibble first, LS Bit first, thus DATA is transmitted starting with the least significant bit of Byte 0, sequentially to the most significant bit of byte (N-1).
LSb MSb 4-7 IDSEL 0,0,0,0 (or 1,0,0,0) LSb MSb 8-35 ADDR 28-bit address IN1 IN1
36-39
MSIZE
S0,S1,S2,S3
IN1
LSb MSb 40-(m-1) m = 40+8*N+ # of wait cycles DATA D0, D1, ..., D(8*N) LSb MSb IN1
(m)-(m+3) (m+4)-(m+7) (m+8)-(m+11) (m+12)-(m+15) (m+16)-(m+19)
TAR0 TAR1 RSYNC TAR0 TAR1
1,1,1,1 1,1,1,1 (float) 0,0,0,0 1,1,1,1 1,1,1,1 (float)
IN1 Float OUT2 OUT2 Float then IN1
In these 4 clock cycles, the aLPC host has driven the aLAD pin to `1'. This is the first part of the bus turnaround. The aLPC host floats the bus, and SST79LF008 takes control of the bus after these 4 cycles, completing bus turnaround. During these 4 clock cycles, the SST79LF008 generates a readysync (RSYNC) indicating that it has received data. In these 4 clock cycles, SST79LF0008 has driven the bus to `1'. This is the first part of the bus turnaround. SST79LF008 floats the bus, and the aLPC host resumes control of the bus after these 4 cycles, completing bus turnaround.
T4-8.0 1320
1. SST79LF008 reads field contents on the falling edge of the present clock cycle 2. Field contents are valid on the falling edge of the present clock cycle, and on the rising edge of the next clock cycle.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
aLCLK aLFRAME aLAD
0 B0 1 B1 1 B2 1 B3 B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3
START 28 29 30 31 32 33
IDSEL 34 35 36 37 38 39
ADDR 40 41 42 43 44
aLCLK aLFRAME aLAD
B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 DATA n+2 n+3 n+4 n+5 n+6 n+7 ADDR 100 101 102 103 104 n MSIZE n+1
aLCLK aLFRAME aLAD
B0 B1 B2 B3 BUSY m-1 m DATA m-4 m-3 m-2 X X X X X X X X X B0 B1 DATA B2
m+1 m+2 m+3 m+4 m+5 m+6 m+7 m+8 m+9 m+10 m+11 m+12
aLCLK aLFRAME aLAD
B0 B1 B2 B3 TAR DATA 1 1 1 1 0 B0 0 0 0 B3
B1 B2 RDY SYNC
m+12 m+13 m+14 m+15 m+16 m+17 m+18 m+19 m+20
aLCLK aLFRAME aLAD
1 B0 1 B1 1 B2 1 B3 TAR B0 START B1 B2 B3
1245 aLPC-MemWr.0
FIGURE
4-9: aLPC Memory Write Cycle The aLPC Host can abort the transaction in progress by taking over and driving aLFRAME# low for at least 4 cycles with a START value of 1,1,1,1 (similar to the standard LPC abort mechanism). Because of the aLFRAME# extended functionality the following limitation for abort timing should be observed: the Host must not drive aLFRAME# in order to abort the transaction when aLFRAME# is asserted low by the SST79LF008 device as well as 4 clocks prior and 4 clocks after this event.
It is possible for SST79LF008 to signal busy status (drive aLFRAME# low) at the falling edge of the very last data bit (clock cycle m-1 on the diagram). This has no effect on the completion of current transaction, i.e., TAR-RSYNC-TAR sequence (clock cycles from m to m+19) is generated without any wait cycles inserted. However, the next LPC transaction must not be started by the Host until the aLFRAME# is returned to high level plus 4 spare clock cycles.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 4.8.4 aLPC Memory Read Operation In the aLPC mode the SST79LF008 device supports AAI and Multi-Byte Memory Read cycles, which allows to load only one address for reading a group of 1, 2, 4, 16, 128TABLE
Clock Cycle 0-3
bytes, 4K, 64K, or 1M-byte of data. These cycles are similar to the standard LPC Firmware Memory Read cycles with the exception of using 4 clocks (instead of 1) to transfer each field.
4-9: aLPC Memory Read Cycle Field Definitions
Field Name START Field Contents 1,0,1,1
SST79LF008
aLAD IN1
Comments aLFRAME# must be active (low) for the part to respond. Only the last four clocks of the start field (before aLFRAME# transitioning high) should be recognized. The START field contents indicate aLPC Firmware Memory Write cycle (value = 1101). Order of bit transfer for this field: LS Bit first ID selects SST79LF0008 device to respond. If the IDSEL field matches the device ID, then that particular device will respond to the whole bus cycle. Valid IDs = 0000 or 0001. Order of bit transfer for this field: LS Bit first These 28 clock cycles make up the 28-bit starting memory address A27-A0. Order of bit transfer for this field: MS Nibble first, LS Bit first: A24,A25,A26,A27, A20,A21,A22,A23, A16,A17,A18,A19, A12,A13,A14,A15, A8,A9,A10,A11, A4,A5,A6,A7, A0,A1,A2,A3 Device will execute multi-byte write for N bytes. Valid field values S = 0, 1, 2, 4, 7 For the respective N = 1, 2, 4, 16 Bytes Order of bit transfer for this field: LS Bit first In these 4 clock cycles, the aLPC host has driven the aLAD pin to `1'. This is the first part of the bus turnaround. The aLPC host floats the bus, and SST79LF008 takes control of the bus after these 4 cycles, completing bus turnaround. During these 4 clock cycles, the SST79LF008 generates a long-waitsync (LWSYNC) indicating that data is not ready, yet. SST79LF008 continues to generate long-wait-sync. During these 4 clock cycles, SST79LF008 generates a ready-sync (RSYNC) indicating that the least-significant bit of the least significant data byte will be sent on the next clock cycle. Data field consists of 8*N clock periods, where N is defined by MSIZE field. The host will insert wait cycles and pause the data stream when aLFRAME# goes low until it returns high, signifying that the chip is ready for more data. Order of bit transfer for this field: LS Nibble first, LS Bit first, thus DATA is transmitted starting with the least significant bit of Byte 0, sequentially to the most significant bit of Byte(N-1).
LSb MSb 4-7 IDSEL 0,0,0,0 (or 1,0,0,0) LSb MSb 8-35 ADDR 28-bit address IN1 IN1
36-39
MSIZE
S0,S1,S2,S3
IN1
LSb MSb 40-43 44-47 48-51 52-(n-5) (n-4)-(n-1) 0,0,0,0 TAR0 TAR1 SYNC 1,1,1,1 1,1,1,1 (float) 0,1,1,0 IN1 Float OUT2 OUT2 OUT2
n-(m-1) m = n+8*N
DATA
D0, D1, ..., D(8*N) LSb MSb
OUT2
(m)-(m+3) (m+4)-(m+7)
TAR0 TAR1
1,1,1,1 1,1,1,1 (float)
OUT2 Float then IN1
In these 4 clock cycles, SST79LF0008 has driven the bus to `1' This is the first part of the bus turnaround. The aLPC host floats the bus, and the aLPC host resumes control of the bus after these 4 cycles, completing bus turnaround.
T4-9.0 1320
1. SST79LF008 reads field contents on the falling edge of the present clock cycle 2. Field contents are valid on the falling edge of the present clock cycle, and on the rising edge of the next clock cycle.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
aLCLK aLFRAME aLAD
1 B0 0 B1 1 B2 1 B3 B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3
START 28 29 30 31 32 33
IDSEL 34 35 36 37 38 39
ADDR 40 41 42 43 44
aLCLK aLFRAME aLAD
B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 ADDR 44 45 46 47 48 49 50 51 52 MSIZE n-5 n-4 n-3 n-2 1 B0 1 B1 1 B2 1 B3 TAR n-1 n
aLCLK aLFRAME aLAD
B0 B1 B2 B3 TAR n n+1 n+2 n+3 n+4 n+5 0 B0 1 B1 1 B2 L_WAIT n+6 n+7 n+8 0 B3 0 B0 SYNC m-4 m-3 1 0 B3 0 B0 0 B1 RDY m-2 m-1 m 0 B2 0 B3
aLCLK aLFRAME aLAD
0 B0 B1 B2 B3 DATA m m+1 m+2 m+3 m+4 m+5 m+6 m+7 m+8 B0 B1 B2 B3 B0 B3 B0 B1 B2 B3
aLCLK aLFRAME aLAD
1 1 1 1 B0 TAR B1 B2 B3
START 1245 aLPC-MemRd.0
FIGURE
4-10: aLPC Memory Read Cycle
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 4.8.5 aLPC I/O Write Operation When the SST79LF008 device is switched into aLPC mode it supports aLPC I/O Write and Read cycles in addition to the aLPC Memory Write and Read cycles previously described. However, in aLPC mode all LPC logical I/O devices are disabled (as all Configuration registers are reset - see Section 23.2). Therefore the only useful aLPC I/O operations are aLPC Write cycles utilized by the aLPC Host to issue aLPC Snooper commands described in Table 4-6. These cycles are similar to the standard LPC I/O Write cycles except 4 clocks (instead of 1) are used to transfer each field. The following exceptions with regards to aLAD and aLFRAME# control are also applied to the aLPC I/O cycles when the Snooper is in IDLE and READY states: * In IDLE and READY states the Snooper tri-states the aLAD line and does not return RSYNC to the Host In READY state the Snooper returns the status of RDY4ALPC bit on aLFRAME# during SYNC phase of the fourth write cycle of the Enable_and_Poll sequence.
*
Examples of I/O Write cycles before and after entry to SWITCHED state (aLPC mode) are shown in Figures 4-11 and 4-12, respectively.
TABLE 4-10: aLPC I/O Write Cycle Field Definitions
Clock Cycle 0-3 Field Name START Field Contents 0,0,0,0
SST79LF008
aLAD IN1
Comments aLFRAME# must be active (low) for the part to respond. Only the last four clocks of the start field (before aLFRAME# transitioning high) should be recognized. The START field contents indicate aLPC Firmware Memory Write cycle (value = 0000). Order of bit transfer for this field: LS Bit first Cycle type field indicates aLPC I/O Write cycle (value - 0010) Order of bit transfer for this field: LS Bit first These 16 clock cycles make up the 16-bit I/O address A15-A0. Order of bit transfer for this field: MS Nibble first, LS Bit first: A12,A13,A14,A15, A8,A9,A10,A11, A4,A5,A6,A7, A0,A1,A2,A3 These 8 clock cycles are used to transmit one Data byte. Order of bit transfer for this field: LS Bit first In these 4 clock cycles, the aLPC host has driven the aLAD pin to `1'. This is the first part of the bus turnaround. The aLPC host floats the bus, and SST79LF008 takes control of the bus after these 4 cycles, completing bus turnaround. During these 4 clock cycles, the SST79LF008 generates a readysync (RSYNC) indicating that data is not ready, yet. In these 4 clock cycles, the aLPC host has driven the bus pin to `1'. This is the first part of the bus turnaround. SST79LF008 floats the bus, and the aLPC host resumes control of the bus after these 4 cycles, completing bus turnaround.
T4-10.0 1320
LSb MSb 4-7 8-23 CYC_TYPE ADDR 0,1,0,0 LSb MSb 16-bit address D0,D1,...D7 LSb MSb 32-35 36-39 40-43 44-47 48-51 TAR0 TAR1 SYNC TAR0 TAR1 1,1,1,1 1,1,1,1 (float) 0,0,0,0 1,1,1,1 1,1,1,1 (float) IN1 Float OUT2,3 OUT2,3 Float then IN1 IN1 IN1
24-31
DATA
IN1
1. SST79LF008 reads field contents on the falling edge of the present clock cycle 2. Field contents are valid on the falling edge of the present clock cycle, and on the rising edge of the next clock cycle. 3. When the Snooper is in IDLE or READY state, aLAD is always floated in SST79LF008 (and SYNC = 1,1,1,1).
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
aLCLK aLFRAME aLAD
0 B0 0 B1 0 B2 0 B3 0 B0 1 B1 0 B2 0 B3 B0 B1 B2 B3 B0 B1 B2 B3
START
CYC_TYP
ADDR
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
aLCLK aLFRAME aLAD
B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 ADDR DATA
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
aLCLK aLFRAME aLAD
1 B0 1 B1 1 B2 1 B3 TAR B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 SYNC Ready for aLPC driven by 79LF008 48 49 50 51 52 TAR
aLCLK aLFRAME aLAD
B0 TAR B1 B2 B3 START
1245 aLPC-IOWrIDLE.0
FIGURE
4-11: aLPC I/O Write Cycle (IDLE or READY state)
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
aLCLK aLFRAME aLAD
0 B0 0 B1 0 B2 0 B3 0 B0 1 B1 0 B2 0 B3 B0 B1 B2 B3 B0 B1 B2 B3
START
CYC_TYP
ADDR
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
aLCLK aLFRAME aLAD
B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 ADDR DATA
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
aLCLK aLFRAME aLAD
1 B0 1 B1 1 B2 1 B3 B0 B1 B2 B3 0 B0 0 B1 0 B2 0 B3 1 B0 1 B1 1 B2 1 B3
TAR
RSYNC
TAR
48
49
50
51
52
aLCLK aLFRAME aLAD
TAR
B0
B1
B2
B3
START 1245 aLPC-IOWrSWITCHED.0
FIGURE
4-12: aLPC I/O Write cycle (SWITCHED state)
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 4.8.6 aLPC Flash Commands When aLPC Mode is enabled (i.e., the aLPC Snooper is in SWITCHED state) all aLPC Memory Write operations are interpreted by the flash command interface. Commands consist of one or more sequential bus write cycles TABLE 4-11: aLPC Bus Flash Command Definitions
Command Read-Array/Reset Read-Device-ID Read Unique ID Read-Status-Register Clear-Status-Register Sector-Erase Block-Erase Program Erase-Suspend Erase-Resume User-Unique-ID Program User-Unique-ID Program-Lockout Enter UNVR (3K OTP) / Enter ENVR Bus Cycles Required 1 First Bus Cycle Oper Write Write Write Write Write Write Write Write Write Write Write Write Addr X X X X X X X X X X X X Data FFH 90H 70H 50H 30H 20H 40H or 10H B0H D0H A5H 85H 60H Write Write Write WA X X WD 00H 76H
T4-11.0 1320
described in Section 4.8.4. The aLPC flash commands are summarized in Table 4-11. For a detailed description of each command, refer to Section 7.3, as aLPC and standard LPC flash command are functionally similar.
Second Bus Cycle Oper Read Read Write Write Write Addr IA X SA BA WA Data ID SRD D0H D0H WD
2
2 1 2 2 2 1 1 2 2 2
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
5.0 POWER, RESET AND CLOCK SOURCES 5.1 Power Planes
SST79LF008 has two power planes: VDD and AVDD. The digital logic and on-chip memory are powered by VDD; the analog circuits in ADC and DAC are powered by AVDD. Both power planes must be applied/removed simultaneously. SST recommends a high frequency 0.1 F ceramic capacitor to be placed as close as possible between each VDD and VSS pin, less than 1cm away from VDD pin. Additionally, a low frequency tantalum capacitor (4.7 f min.) from VDD to VSS should be placed on the common power/ground net as close as possible to the chip. SST recommends a high frequency 0.1 F ceramic capacitor to be placed as close as possible between each AVDD and AVSS pin, less than 1cm away from AVDD pin. Additionally, a low frequency tantalum capacitor (4.7 f min.) from AVDD to AVSS should be placed on the common analog power/ground net as close as possible to the chip. Note also that a high frequency 1 F ceramic capacitor must be placed as close as possible between SST79LF008 internal regulator output VREG and VSS pin, less than 1 cm away from VREG pin. For correct SST79LF008 operation all power pins must be connected to the respective power/ground planes, see Section 2.1, "Pin Descriptions".
5.2 Reset Sources
SST79LF008 has the following reset sources: 1. Power-On reset (POR) 2. External Chip reset (RESET# pin) 3. Brown-out detection reset (BOR) 4. Watchdog timer (WDT) reset 5. aLPC Soft reset 6. LPC Soft reset 7. 8051 Soft reset 8. Configuration Soft reset 9. LPC Interface reset (LRESET# pin)
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE
Reset Source POR External Reset BOR WDT reset aLPC Soft Reset
5-1: SST79LF008 Reset Sources
Restart Idle PD 8051 code Wake Wake after reset Maskable up up Yes1 Yes1 Yes1 Yes1 Yes1 No No Yes Yes No Yes Yes Yes Yes Yes Yes Yes No Yes Yes
Reset Mechanism VDD is powered up RESET# pin is asserted low VDD is below Brown-Out threshold Watchdog timer underflow
Reset Modules The SST79LF008 chip The SST79LF008 chip The SST79LF008 chip The SST79LF008 chip
(a) Entry to aLPC mode via aLPC The SST79LF008 chip, Switch_and_Reset sequence except the aLPC snooper (b) Exit from aLPC mode via aLPC Exit_and_Reset sequence Force LPC Soft Reset command received via LPC bus 8051 MCU, selected MMCRs, and Configuration registers; clear SFSC[2] (OVERLAY) bit
LPC Soft Reset 8051 Soft Reset Configuration Soft Reset
Yes2
Yes
Yes
Yes
Transition of SOFTRST = SFCS[3] 8051 MCU and bit from `0' to `1' selected MMCRs; clear SFSC[2] (OVERLAY) bit Transition of Bit 0 in Chip Control register 0 from `0' to `1' Configuration registers The LPC bus interface and flash block locking registers
Yes2
No
N/A
N/A
No No
No No
N/A Yes
N/A Yes
T5-1.0 1320
External LPC LRESET# pin is asserted low Interface reset
1. Start address and OVERLAY bit state is determined by ENVR contents as described in Section4.4.5. 2. Start address is 0000H regardless of ENVR contents and OVERLAY bit is always cleared.
The SST79LF008 reset block diagram is shown on Figure 5-1. POR, External Reset, BOR, and WDT resets are internally "or-ed" to form an internal reset signal to the whole SST79LF008 chip. This signal is asserted as soon as any of the above reset sources is asserted and will be deasserted only when none of them is asserted. The 16-bit reset extender counter guarantees that the chip will be held in reset state for at least 65,536 clocks of RCLK after all these reset sources are de-asserted. The extended reset signal applied to aLPC Snooper and "or-ed" with aLPC Soft reset to form a flash memory reset. The 7-bit configuration extender counter keeps 8051 MCU and other peripheral modules in reset state for 128 clocks of RCLK, while the internal configuration is performed in hardware. After the configuration extender is expired and the internal Chip Logic Reset signal is de-asserted, all SFRs (see Section 3.4), MMCRs (see Section 3.5), flash block locking registers (see Section 7.6), and configuration registers (see Section 23.2) contain their respective reset values. The 8051 program execution will restart from either address 0000H or F000H (BootRom) depending on the ENVR contents as described in Section 4.5.
The 8051 firmware Soft Reset affects the 8051 MCU core including all SFRs, and selected MMCRs as specified in Section 3.5. After the 8051 Soft reset the OVERLAY bit is always cleared. Thus, the 8051 program execution will restart from address 0000H. The LPC Soft reset affects the 8051 MCU core including all SFRs, selected MMCRs as specified in Section 3.5, and all Configuration registers. After the LPC Soft reset the OVERLAY bit is always cleared. Thus, the 8051 program execution will restart from address 0000H. The Configuration Soft reset affects configuration registers only; it does not restart 8051 code execution. The LPC Interface reset signal initializes LPC interface state machine (including Serialized IRQ, and CLKRUN# mechanisms), and resets flash memory command sequence described in Section 7.3 as well as all flash block locking registers described in Section 7.6. The LPC reset does not restart 8051 code execution. Note. The internal SRAM is not affected by any type of reset. On power up, the SRAM content is indeterminate.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
Reset aLPC Snooper Reset Flash memory POR BOR WDT Reset Ext. Reset Reset Extender (16-bit RCLK counter) Configuration Extender (7-bit RCLK counter) Chip Logic Reset (LPC Interface, 8051 MCU, and all peripheral modules and registers)
aLPC Soft Reset
8051 Soft Reset LPC Soft Reset Configuration Soft Reset
Reset 8051 MCU and selected MMCRs
Reset Configuration registers
Ext. LPC Reset
Reset LPC Interface
1245 RstBlk.0
FIGURE
5-1: Reset Block Diagram
5.2.1 Power-On Reset The SST79LF008 provides an internal power-on reset circuit, which generates Power-On Reset when VDD power is applied. The POR is extended internally until ring oscillator clock is stabilized and counted at least 65,536 times. See Figure 5-1. However, the 32.768 KHz oscillator has much larger power on stabilization time. Therefore, accuracy of any module in the XCLK domain (see Table 5-3) is not guaranteed immediately after POR. If necessary the external RC circuitry can be used to additionally extend POR, see Figure 5-2, or 8051 firmware can implement software delay before using XCLK controlled devices. The POF flag in PCON register is set to indicate that Power-On Reset has occurred, see Section 11.4.
VDD
VDD
SST79LF008
RESET#
+ -
VSS
1245 ExtResetCircuit.0
FIGURE
(c)2006 Silicon Storage Technology, Inc.
5-2: External Reset Circuit
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 5.2.2 External Reset An External reset, derived from the external circuitry connected to the RESET# pin of SST79LF008, will reset the entire chip. In order to properly reset the device, a logic level low must be applied to the RESET# pin for at least 48 cycles of 8051 core clock (CCLK) once VDD power is already applied. External reset can not be masked. If External reset occurs when the chip is in Idle or Power Down mode, it will cause the chip to exit the respective mode. 5.2.3 Brown-out Detection Reset The device includes a Brown-Out detection circuit to protect the system from severe supply voltage VDD fluctuations. When VDD drops below the brown-out voltage 5.2.3.1 Reset Control Register (RSTCON)
Location Read 7F2EH Write Reset X X X X X 0 7 6 5 4 3 2 WDTPOL 1
WDTRSTE N
threshold, the detector circuit generates a brown-out reset to reset the whole device. The BOR is de-asserted automatically after VDD exceeds the brown-out voltage threshold. Brown-out reset can be masked via BOREN bit in RSTCON register (by default BOR is enabled). If BOR occurs when the chip is in Idle mode, it will cause the chip to exit the respective mode. BOR is not generated when chip is in Power Down mode. The BOF flag in PCON register () is set when brown-out condition is detected, provided BOR is enabled. See Section 11.4.
0 BOREN 1
0
Symbol X WDTPOL
Function Not implemented Not defined WDT Output Polarity control bit 1: WDT output is High Active (when WDT underflows) 0: WDT output is Low Active (when WDT underflows) WDT Reset Enable bit 1: Enable WDT Reset 0: Disable WDT Reset BOR Enable bit (When in Power Down mode, BOR is disabled regardless of this bit state.) 1: Enable BOR 0: Disable BOR MCU held in reset, until aLPC exit sequence terminates aLPC mode. After Exit_and_Reset sequence is received the SST79LF008 chip is reset again. The reset extender does not affect aLPC Soft reset duration. The aLPC Host is required to provide at least 8 spare aLPC clock cycles after the end Switch_and_Reset or Exit_and_Reset sequence. For the aLPC sequences details, see Section 4.8. The aLPC Soft reset can not be masked. If it occurs when the chip is in Idle or Power Down mode, the respective mode is terminated.
WDTRSTEN
BOREN
5.2.4 Watchdog Timer (WDT) Reset Watchdog Timer (WDT) reset is generated when WDT underflows (i.e., when firmware failed to reload WDT within the programmed watchdog interval). WDT reset affects the entire device. It can be masked by WDTRSTEN bit in RSTCON register (by default WDT reset is disabled). In addition WDT controls allow firmware to stop WDT completely, or only in Power Down mode. For more WDT operation details, see Section 10.0. 5.2.5 aLPC Soft Reset A Switch_and_Reset sequence, sent over an aLPC bus, resets the whole chip with the exception of aLPC Snooper. Then the SST79LF008 device will enter aLPC mode with flash memory bus owned by the aLPC Host and 8051
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 5.2.6 LPC Soft Reset A Force LPC Soft Reset command sent over LPC bus will reset the 8051 MCU core, including all SFRs, selected MMCRs and all Configuration registers. After this command flash memory bus is owned by the LPC Host, and 8051 is held in reset state, until a Release LPC Soft Reset command is received. The reset extender and configuration extender counters do not affect LPC Soft reset. See Section 7.3.10 for command details and Section 3.5 for the list of affected MMCRs. The LPC Soft reset can be masked via LRSTCOREENB bit in LPC bus monitor register described in Section 23.1. If LPC Soft reset occurs when the chip is in Idle or Power Down mode, the respective mode is terminated. 5.2.7 8051 Firmware Soft Reset A transition from 0 to 1 of SFCS[3] (SOFTRST) bit will generate an internal reset signal, which resets the 8051 MCU core and selected MMCRs. The reset extender and configuration extender counters do not affect 8051 Soft reset. See Section 3.5 for the list of affected MMCRs. 5.2.8 Configuration Soft Reset When bit 0 of the chip control register 0 transitions from 0 to 1, only the configuration registers are reset. For more details, see Section 23.2. 5.2.9 LPC Interface Reset LPC Interface reset is controlled by the LRESET# input. When the LRESET# signal is active low, the SST79LF008 device ignores the LFRAME# and LCLK inputs, and tristates the address/data signals of LPC bus LAD[3:0], as well as SERIRQ and CLKRUN# outputs. The LRESET# resets LPC interface state machine (including SERIRQ and CLKRUN# mechanisms), flash command sequencer and flash block locking registers described in Section 7.6. During this process, the STICKY_LK bit in SFSEC register is also cleared. The reset extender and configuration extender counters do not affect LPC Interface reset. The LRESET# can not be masked, and it generates an interrupt to 8051, which can be configured as a wake up event from Idle or Power Down mode. If LRESET# signal is activated while flash memory Erase is in progress, the SRI hardware automatically suspends Erase operation and switches flash memory to read array mode during the LPC Host read access after LRESET# is de-asserted. LPC read operation within any flash sector/ block, other than the suspended one, would complete normally in this case. The erase operation will automatically resume on completion of the LPC Host read. If LPC reset occurs when flash bus was turned over to the LPC Host
(c)2006 Silicon Storage Technology, Inc. S71320-01-000 10/06
(using mechanism (a) or (b) described in Section 4.3), it is LPC Host software and 8051 firmware's responsibility to restore 8051 flash bus ownership after LRESET# is deasserted and erase operation is finished. If LRESET# signal is activated after Force LPC Soft Reset command, the flash bus will be automatically released to 8051, and 8051 will restart code execution when LRESET# is de-asserted. In a case when erase operation was initiated during LPC Soft Reset, and aborted by LRESET# assertion (i.e., mechanism (c) in Section 4.3 was used), the 8051 will not be able to properly fetch flash memory contents, making code execution results unpredictable. Therefore mechanism (c), is not recommended for flash update unless flash memory is blank or corrupted. The LRESET# signal has no effect in aLPC mode.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
5.3 Clock Sources
5.3.1 Clock Input Options The SST79LF008 has several clock sources which are listed in Table 5-2. TABLE 5-2: SST79LF008 Clock Sources
Frequency 10-20MHz 4-16MHz Up to 33 MHz 32.768KHz Up to 33MHz Up to 5MHz Destination 8051 CPU and core peripherals PLL, 8051 CPU and core peripherals 8051 CPU and core peripherals Hibernation timer, Timer0, Timer1, Watchdog timer, Fan tachometer, and PWM LPC Bus Interface aLPC Bus Interface
T5-2.0 1245
Clock Source Internal Ring Oscillator Clock (RCLK) External Clock (ECLK) signal Internal PLL-Generated Clock (PCLK), derived from ECLK External crystal connected to the internal oscillator circuit (XCLK) External LPC Clock (LCLK) External aLPC Clock (aLCLK)
Internal clock sources include Ring Oscillator and PLL, which, however, depends on external clock ECLK. External clock sources include ECLK as well as LPC clocks LCLK and aLCLK. The 32.768 kHz clock is generated by the circuitry which combines an on-chip oscillator and an external crystal as shown on Figure 5-3. 5.3.1.1 Crystal Oscillator
OSC1 RF
OSC2
RS
C1
C2
Boundry internal to chip
1245 CryOscCir.0
FIGURE TABLE
RF 10M
5-3: Crystal Oscillator Circuit
5-3: Crystal Oscillator Circuit Components
RS 0 -- 200K C1,C2 10 -- 35pF Crystal Frequency 32.768KHz
T5-3.0 1245
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 5.3.2 Clock Selection Control and Clock Domains The 8051 CPU and core peripherals clock (CCLK) are derived from three different clock sources--the on-chip ring oscillator (RCLK), the PLL clock (PCLK), and the external clock source (ECLK). The 8051 can be programmed to switch the clock source during normal code execution. The 8051 clock source can be selected through the Clock Source Control Register (CLKSRCCON). In addition peripheral modules Time0, Timer1, and PWM have their own clock selection control registers described in Section 10.0. The 8051 core clock, as well as some peripheral clocks, are stopped when 8051 enters either Idle mode or Power Down mode. for PCON register description, see Section 11.4.
1 ECLK PD PLLSTOP Ring Oscillator ROSCEN EN
CLKSEL_8051 POWERGOOD
MCLK
PLL ST
1 CCLK 0 PD IDL 8051 core clock 8051 CPU clock
PCLK
0
RCLK
XCLK X'tal EN LCLK Boundry internal to chip XTALEN PD
Crystal Oscillator clock Peripheral clock LPC clock
1245 ClockSel.0
FIGURE 5-4: SST79LF008 Clock Selection The SST79LF008 clock usage and clock domains are summarized in the Table 5-4. TABLE
MODULE 8051 Timer 0/1 Timer 2 Hibernation timer WDT Fan Tachometer PWM ADC DAC PWM LED UART SPI SMBus PS/2 GPIO LPC Interface
5-4: Clock Domains for SST79LF008 Modules
Clock Domain 8051 CPU clock 8051 core clock Peripheral clock 8051 core clock Crystal Oscillator clock Peripheral clock Peripheral clock 8051 core clock Crystal Oscillator clock 8051 core clock 8051 core clock Crystal Oscillator clock 8051 core clock 8051 core clock 8051 core clock 8051 core clock 8051 core clock LPC clock Clock status in Idle mode stop run run run run run run run run run run run run run run run run X1 Clock status in Power Down stop stop stop stop run run/stop depends on (WDTCSR[7]) run/stop depends on (FANTIMEBASE[7:6]) stop run stop stop run stop stop stop stop stop (retain I/O state) X1
T5-4.1245
1. LPC clock status is controlled by the external LPC Host, it is not affected by 8051 Idle or Power Down mode.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 5.3.2.1 Clock Source Control Register (CLKSRCCON)
Location Read 7F27H Write Reset X X 7 6 5 CLKSEL_ 8051 0 4 ROSCEN 1 3 PLLOK 0 2 XTALEN 1 1 PLLSTOP 0 0 ECLKOK 0
Symbol X CLKSEL_8051
Function Not implemented Not defined 8051 clock source selection bit 1: 8051 Clock source CCLK = MCLK (i.e., either PCLK or ECLK) 0: 8051 Clock source CCLK = RCLK Ring Oscillator Enable bit The 8051 firmware can read/write this bit. It is also reset by hardware on entry to Power Down mode, and set on wake up from Power Down mode Enable Ring oscillator 0: Stop Ring oscillator PLL status bit This bit is set when PLL output signal is stabilized. If firmware attempts to select PCLK as 8051 core clock source when this bit is cleared, hardware uses RCLK instead, until PLLOK is set. Only after PLLOK is set 8051 core clock is switched to PCLK. An interrupt is generated when PLLOK bit changes from 0 to 1. 1: PLL is stabilized (the PLL stabilization counter reaches 3F00H = 16,128) 0: PLL is not stabilized because of any of the following 3 conditions PLL stopped (PLLSTOP =1, PLL stabilization counter is reset) ECLK stopped (ECLKOK = 0, PLL stabilization counter is reset) PLL stabilization time has not expired (PLLSTOP = 0, ECLKOK = 1, PLL stabilization counter is running but has not reached 3F00H, yet). This bit and PLL stabilization counter are cleared in hardware on entry to Power Down mode.
ROSCEN
PLLOK
XTALEN
Crystal Oscillator Enable bit 1: Enable 32.768KHz crystal oscillator 0: Disable 32.768KHz crystal oscillator PLL control and MCLK selection bit 1: Select MCLK = ECLK (PLL module is stopped, stabilization counter is reset) 0: Select MCLK = PCLK (PLL module is running) External clock ECLK status bit This bit is set when ECLK is applied. If firmware attempts to select ECLK as 8051 core clock when this bit is cleared, the hardware uses RCLK instead, until ECLKOK is set. Only after ECLKOK is set to 8051 core clock is switched to ECLK. An interrupt is generated when ECLKOK changes from 0 to 1 or from 1 to 0 1: ECLK is running 0: ECLK has stopped
PLLSTOP
ECLKOK
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 5.3.2.2 PLL M Value Register (PLLM)
Location Read 7F35H Write Reset X X 1 0 0 0 1 0 7 6 5 PLLM5 4 PLLM4 3 PLLM3 2 PLLM2 1 PLLM1 0 PLLM0
5.3.2.3 PLL PS Value Register (PLLPS)
Location Read 7F36H Write Reset X X 1 1 0 0 1 0 7 6 5 PLLP1 4 PLLP0 3 PLLS3 2 PLLS2 1 PLLS1 0 PLLS0
Symbol X PLLM[5:0], PLLP[1:0], PLLS[3:0]
Function Not implemented Not defined PLL Output frequency control* FPLLO = FPLLI * m/(p*s) m = 2*(M+2) p = (P+1) s = 2*(S+2)
P 0 0 0 1 1 1 2 2 2 3 3 3 3 3 M 34 34 30 34 34 30 34 34 30 38 38 34 34 30 S 7 4 2 7 4 2 7 4 2 7 4 2 4 2 FPLLO (MHz) (PCLK) 16 24 32 16 24 32 16 24 32 15.9089 23.8633 32.2155 24 32
T5-4.1245
FPLLI (MHz) (ECLK) 4 4 4 8 8 8 12 12 12 14.318 14.318 14.318 16 16
5.3.3 Clock Switching after Power On and Reset When SST79LF008 is powered on, the default clock source is always the internal ring oscillator. The RCLK continues to be used until all of the following events have taken place. 1. The 65,536 + 128 counts of RCLK are completed 2. ECLK is running
3. PWRGOOD pin is high 4. RCLK is not selected by firmware as the core clock (i.e., CLKSEL_8051 = 1) 5. The PLL output clock (if enabled), has been through 16,128 (3F00H) counts
* When changing PLL output frequency (i.e. changing PLLM and/or PLLPS register) PCLK must not be selected as 8051 core clock When changing PLL output frequency (i.e. changing PLLM and/or PLLPS register) PCLK must not be selected as 8051 core clock
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information If all these five conditions are satisfied, a smooth transition from ring oscillator clock to the desired clock source ECLK or PCLK will automatically take place. Until then, the ring oscillator clock is supplied to the 8051 core. The 8051 starts execution as soon as it is released from reset using the oscillator clock, and then switches to another clock later on at run time. See Figure 5-4. The described clock selection procedure is followed after External reset, WDT reset and aLPC Soft reset. Then, SST79LF008 will use the selected clock as long as software clock selection is not changed, ECLK is available, and PWRGOOD signal is high. 5.3.3.1 Power Good Signal PWRGOOD is a signal that indicates the system power is `good'. The SST79LF008 device uses this signal as an external indicator of the availability of the ECLK clock. When PWRGOOD goes low, it indicates that the ECLK will be going away. Therefore SST79LF008 will automatically switch to internal ring oscillator as the clock source. In this case the ECLK must be available for at least two full cycles after PWRGOOD becomes low.
After power up RCLK is the default clock source for 8051 core
SST79LF008 is held in reset state for 65,536 RCLK clocks
8051 is held in reset state for additional 128 RCLK clocks while hardware completes internal configuration (using RCLK)
8051 starts executing program (using RCLK) Switch From RCLK to ECLK Switch From RCLK to PCLK
Running from RCLK, 8051 sets CLKSEL_8051=1; PLLSTOP=1
Running from RCLK, 8051 f/w sets CLKSEL_8051=1; PLLSTOP=0
Hardware switches to ECLK after two ECLK clocks Switch From ECLK to RCLK Switch From ECLK to PCLK Switch From PCLK to RCLK
Hardware switches to PCLK after 3F00H of PCLK counts Switch From PCLK to ECLK
Running from ECLK, 8051 sets CLKSEL_8051=0
Running from ECLK, 8051 sets PLLSTOP=0
Running from PCLK, 8051 sets CLKSEL_8051=0
Running from ECLK, 8051 sets PLLSTOP=1
Hardware switches to RCLK after two RCLK clocks
Hardware switches to RCLK, then switches to PCLK after 3F00h PCLK counts
Hardware switches to RCLK after two RCLK clocks
Hardware switches to ECLK after two ECLK counts
1245 PwrON_ClkSWT.0
FIGURE
5-5: Power-On Sequence and Core Clock Switching
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 5.3.4 Clock Switching in Low Power Modes The SST79LF008 device has two low power modes: idle and Power Down mode. Idle mode is entered by setting IDL bit in PCON register (Section 11.4). In idle mode the internal clock is gated off to the 8051CPU. In this mode, Clock selection controls cannot be changed and all peripheral modules continue to operate normally. Idle mode can be terminated by one of the reset events (see Table 5-2), or by any enabled interrupt (see Table 8-1). In any case the IDL bit is cleared in hardware on exit from idle mode. Clock selection, in the case when idle mode is terminated by a reset event, follows the procedure described in the Section 5.3.3. If Idle mode is terminated by an interrupt, 8051 uses the current clock selection and executes a call to the respective interrupt vector within one machine cycle after interrupt request is asserted. On return from the interrupt, the next instruction executed is the one following the instruction that sets IDL bit. Power Down mode is entered by setting PD bit in PCON register (Section 11.4). In this mode the clock is stopped for 8051 CPU and most of the peripherals. At this time only modules in Crystal Oscillator and LPC Interface domains may continue to operate (see Table 5-3). After 8051 enters into Power Down mode, hardware stops PLL and Ring Oscillator automatically. Power Down mode can be terminated by one of the reset events (see Table 5-2), or by any enabled wake up event (see Table 8-1). In any case PD bit is cleared in hardware on exit from Power Down mode. Clock selection, in the case when Power Down mode is terminated by a reset event, follows the procedure described in Section 5.3.3. Clock selection, in the case when Power Down mode is terminated by a wake event, is shown on Figure 5-4. After waking up from Power Down mode, the 8051 always uses RCLK as a core clock, and executes a call to the respective wake up interrupt vector within two machines cycles after the wake event. On return from the interrupt, the next instruction executed is the one following the instruction that sets PD bit. Independent of code execution flow, 8051 is then automatically switched by clock selection hardware to another clock source, such as ECLK or PCLK, if the source is stable and was selected by software before Power Down mode entry.
8051 Enters into Power Down Mode
Hardware automatically stops PLL and Ring Oscillator
Power Down Mode
Enabled Wake up event terminates Power Down mode and starts Ring Oscillator
8051 wakes up from Power Down Mode and uses RCLK automatically CLKSEL_8051 = 1 & PLLSTOP = 1 CLKSEL_8051 = 1 & PLLSTOP = 0
Hardware switches to ECLK after two ECLK clocks
Hardware switches to PCLK after 3F00H of PCLK counts
1245 ClkSwt_Wakeup.0
FIGURE
5-6: Clock Switching after Waking up from Power Down Mode
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
6.0 8051 EMBEDDED MICROCONTROLLER
The SST79LF008 device includes a high performance 8051 embedded microcontroller unit (MCU) as shown on Figure 1-1. 6.2.2 17-Bit Contiguous Addressing Mode In 17-bit contiguous addressing mode, code and data access utilizes expanded 17-bit program counter and 17-bit data pointer; several branching and transfer instructions are modified as described below. In this mode the MCU can access up to 128 KByte of program and data memory. Selection of this mode is controlled by AM1 bit in ACON register, See also "6.5.1 Address Control Register (ACON)" . AM1 = ACON[1] = 1: Select 17-bit Contiguous Addressing Mode AM1 = ACON[1] = 0: Select 16-bit Addressing Mode (reset value) 6.2.2.1 8051 Instruction Set Modifications All instruction opcodes are the same for the 16-bit and 17bit addressing modes. The operand size and encoding is also the same except for the ACALL, AJMP LCALL and , LJMP branch instructions and a MOV DPTR, #data instruction. These unique instructions will require the compiler to generate additional operands in 17-bit addressing mode relative to the conventional 16-bit addressing mode. Therefore 17-bit addressing mode support requires an assembler, compiler and linker to be specifically designed to properly handle the modified length of the above instructions. The number of machine cycles per instruction may also be different because in 17-bit mode all branch instructions operates over entire 17-bit program counter, and all instructions which utilize the data pointer operates over 17-bit expanded DPTR = DPX[0]+DPH+DPL. However, changes in the number of machine cycles are transparent for the assembler and compiler. The 8051 instructions modified in 17-bit addressing mode are specified in Table 6-1, which provides encoding, and byte numbers, as well as execution details for each instruction. The instruction assumes that extended 2 KByte stack mode is selected, see Section 6.5. Note, however, that 17bit contiguous addressing mode can be also used with traditional 8051 256 Byte stack; in this case extended stack pointer ESP:SP in Table 6-1 is replaced by standard stack pointer SP .
6.1 8051 MCU Enhancement
The 8051 embedded controller in SST79LF008 provides the following major improvements over the traditional 8051 controller: * Increased performance: Adopts a selectable 6- or 3- clock machine cycle in lieu of the conventional 12-clock machine cycle, and supports up to 33 MHz operating frequency Increased program address space: Up to 128 KByte instead of conventional 64 KByte Increased on-chip SRAM: 2 KByte plus standard 256 Byte data memory Increased stack address space: Up to 2 KByte instead of conventional 256 Byte stack Dual Data Pointers: provide extra programming flexibility for 8051 code development Power-saving Operation: Idle and Power Down modes with multiple maskable wake-up sources Programmable clock source: internal ring oscillator (RCLK), external input clock (ECLK), or PLL clock (PCLK derived from ECLK, programmable frequency)
* * * * * *
6.2 8051 Addressing Modes
The SST79LF008 supports two different addressing modes selectable by the AM1 bit in the ACON register. The 8051 core operates in either the traditional 8051 16-bit address mode (64 KByte address space) or in a 17-bit contiguous address mode (128 KByte address space). 6.2.1 16-Bit Addressing Mode In 16-bit addressing mode, code and data access is similar to the traditional 8051 memory access; all MCU instructions are opcode compatible and have identical byte count with the conventional 8051 controller. In this mode the MCU can access up to 64 KByte of program and data memory. The SST79LF008 defaults to 16-bit addressing mode following any reset event, which restarts 8051, as specified in Table 5-2.
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Advance Information TABLE 6-1: 17-bit Addressing Mode-Specific Instructions
INSTRUCTION CODE MNEMONIC ACALL addr19 D7 D6 D5 D4 D3 D2 D1 D0 a18 a17 a16 1 0 0 a7 a6 0 1 a15 a14 a13 a12 a11 a10 a9 a8 a5 a4 a3 a2 a1 a0 NUMBER of BYTES 3 OPERATION (PC) <- (PC) + 3 (ESP:SP) <- (ESP:SP) + 1 ((ESP:SP)) <- (PC7-0) (ESP:SP) <- (ESP:SP) + 1 ((ESP:SP)) <- (PC15-8) (ESP:SP) <- (ESP:SP) + 1 ((ESP:SP)[0]) <- (PC16) (PC16-0) <- addr16-0 AJMP addr19 a18 a17 a16 0 0 0 a7 a6 a5 INC DPTR 1 0 0 0 1 0 LCALL addr24 0 1 3 (PC) <- (PC) + 3 (PC16-0) <- addr116-0 1 4 (DPTR) <- (DPTR) + 1 (PC) <- (PC) + 4 (ESP:SP) <- (ESP:SP) + 1 ((ESP:SP)) <- (PC7-0) (ESP:SP) <- (ESP:SP) + 1 ((ESP:SP)) <- (PC15-8) (ESP:SP) <- (ESP:SP) + 1 ((ESP:SP)[0]) <- (PC16) (PC16-0) <- addr16-0 LJMP addr24 0 0 0 0 0 01 0 4 (PC16-0) <- addr16-0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 MOV DPTR, #data24 1 0 0 a4 a3 a2 a1 a0 1 0 00 0 4 (DPTR) <- (#data16-0) DPX[0] <- #data16 DPH <- #data15-8 DPL <- #data7-0 1 (PC16) <- ((ESP:SP)[0]) (ESP:SP) - 1 (PC15-8) <- ((ESP:SP)) (ESP:SP) - 1 (PC7-0) <- ((ESP:SP)) (ESP:SP) - 1 RETI 0 0 1 1 0 01 0 1 (PC16) <- ((ESP:SP)[0]) (ESP:SP) - 1 (PC15-8) <- ((ESP:SP)) (ESP:SP) - 1 (PC7-0) <- ((ESP:SP)) (ESP:SP) - 1
T6-1.1320
a15 a14 a13 a12 a11 a10 a9 a8 a4 a3 a2 a1 a0 0 1 0 0 01 01 1 0
a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 RET 0 0 1 d4 d3 d2 d1 d0 0 0 01 0
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Advance Information
6.3 8051 Machine Cycle Control
For any 8051 core clock CCLK source specified in Section 5.3.2, the number of CCLK clocks within each instruction cycle can be selected by clock mode bit in 8051 clock control register. 6.3.1 Clock Control Register (CLKCON)
Location SFR AFH 7 Read Write Reset X 6 X 5 X 4 X 3 SPR2 0 2 CLKMD 1 1 T1SEL32K 0 0 T0SEL32K 0
Symbol X SPR2
Function Not implemented Not defined SPI clock Rate select bit 2 This bit together with SPR[1:0] bits controls SPI clock rate in master mode (see Section 12.4.1) 8051 clock Mode control bit 1: 6-clock mode (6 clocks in one instruction cycle) 0: 3-clock mode (3 clocks in one instruction cycle) Timer 1 clock Selection bit for event counter function 1: Timer 1 uses the 32.768KHz clock as event counter clock 0: Timer 1 uses external signal on the T1 input pin as event counter clock Timer 0 clock Selection bit 1: Timer 0 uses the 32.768KHz clock as event counter clock 0: Timer 0 uses external signal on the T0 input pin as event counter clock
CLKMD
T1SEL32K
T0SEL32K
6.4 8051 Dual Data Pointers
SST79LF008 has two 17-bit data pointers sharing the same addresses in SFR space: both DPL registers share address 82H, both DPH registers share address 83H, and both DPX registers share address 93H. The DPTR selection bit (DPS) in AUXR1 register determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is selected, and when DPS = 1, DPTR1 is selected. Quick 6.4.1 Auxiliary Register (AUXR1)
Location SFR A2H Read Write Reset 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 DPS 0
switching between the two data pointers can be accomplished by a single INC AUXR1 instruction. When switching between DPTR0 and DPTR1, all three DPX, DPH and DPL registers are switched respectively. The non-selected DPTR registers retain the values they have prior to switch. Refer to Figure 6-1 for illustration of dual data pointer organization.
Symbol X DPS
Function Not implemented Not defined DPTR Registers Selection bit 1: DPTR1 is selected 0: DPTR0 is selected
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Advance Information 6.4.2 Data Pointer Low Register (DPL)
Location SFR 82H Read Write Reset 7 DPL7 0 6 DPL6 0 5 DPL5 0 4 DPL4 0 3 DPL3 0 2 DPL2 0 1 DPL1 0 0 DPL0 0
Symbol DPL[7:0]
Location SFR 83H 7 DPH7 0
Function Low byte of DPTR
6 DPH6 0 5 DPH5 0 4 DPH4 0 3 DPH3 0 2 DPH2 0 1 DPH1 0 0 DPH0 0
6.4.3 Data Pointer High Register (DPH)
Read Write Reset
Symbol DPH[7:0]
Location SFR 93H 7 X
Function High byte of DPTR
6 X 5 X 4 X 3 X 2 X 1 X 0 DPX0 0
6.4.4 Data Pointer Extended Register (DPX)
Read Write Reset
Symbol X DPX[0]
AUXR1[0] DPS
Function Not implemented Not defined Most significant bit of DPTR when in 17-bit addressing mode
DPTR DPTR1
DPS=1 DPS=0
DPTR=1 DPTR=0 DPX 93H DPH 83H DPL 82H
DPTR0
External Data Memory
1245 DualDataPoint_6.0
FIGURE
6-1: Dual Data Pointer Organization
6.5 8051 Stack Extension
The conventional 8051 stack is limited to 256Byte internal RAM. The SST79LF008 MCU provides either this conventional stack, or an extended 2 KByte stack (11-bit stack address). When extended stack is enabled by setting the Stack Address (SA) bit in the ACON register, the 2 KByte expanded RAM (XRAM) becomes the memory space used by all instructions that affect the stack. The 11-bit address is formed by concatenating the lower 3 bits of the Extended Stack Pointer (ESP), and the 8-bit Stack Pointer (SP).
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When the SA bit is set, any overflow of SP from FFH to 00H will increment the ESP by 1, and any underflow of SP from 00h to FFH will decrement the ESP by 1. When SA = 0, ESP is ignored, but still read/write accessible, and SP is used as a conventional stack pointer.
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Advance Information 6.5.1 Address Control Register (ACON)
Location SFR 9DH Read Write Reset 7 X 6 X 5 X 4 X 3 X 2 SA 0 1 AM1 0 0 X
Symbol X SA
Function Not implemented Not defined Extended Stack Address Mode Enable bit 1: All stack instructions will utilize the 11-bit stack pointer ESP:SP formed by concatenating the 3 least significant bits of ESP register with the SP register 0: All stack instructions will utilize the traditional 8-bit 8051 SP register Address Mode Control bit. 1: 17-bit Contiguous Addressing Mode (128 KByte 8051 flash area and 896 KByte/7.0Mbit BIOS flash area) 0: 16-bit Addressing Mode (64 KByte 8051 flash area and 960 KByte/7.5Mbit BIOS flash area)
7 X 6 X 5 X 4 X 3 X 2 ESP2 0 1 ESP1 0 0 ESP0 0
AM1
6.5.2 Extended Stack Pointer Register (ESP)
Location SFR Read Write 9BH Reset
Symbol X ESP[2:0]
Function Not implemented Not defined Extended Stack Pointer This register contains the upper 3 bits of the 11-bit extended stack pointer. 11-bit stack pointer allows a stack depth of 2 KBytes. Note that as the stack reaches the top of the 2 KByte XRAM, it will wrap around to XRAM location 0.
7 SP7 0 6 SP6 0 5 SP5 0 4 SP4 0 3 SP3 0 2 SP2 1 1 SP1 1 0 SP0 1
6.5.3 Stack Pointer Register (SP)
Location SFR 81H Read Write Reset
Symbol SP[7:0]
Function Stack Pointer The stack pointer identifies current location of the stack. The stack pointer is incremented before every push operation (decremented after every pop operation). After reset SP defaults to 07H, and the stack starts at Internal RAM location 07H. Once the 11-bit stack is enabled (SA = 1), this register is combined with the extended stack pointer (ESP) to form the 11-bit address, and the stack will start at XRAM location 07H. Of course, software can relocate the stack to different portion of RAM as desired.
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Advance Information
7.0 LPC INTERFACE
The SST79LF008 communicates with the host through the LPC bus. The SST79LF008 LPC interface implementation complies with LPC Interface Specification, Rev. 1.1, and always supports LPC I/O Read/Write cycle types. When LPCMODE bit of LPCMON register is `0', the SST79LF008 responds to Multi-Byte Firmware Memory Read/Write cycles on the LPC bus, and LPC Memory cycles are ignored. When LPCMODE bit of LPCMON register is `1', the SST79LF008 responds to Single-Byte LPC Memory Read/Write cycles on the LPC bus, and LPC Firmware Memory cycles are ignored. SST79LF008 utilizes all required LPC signals: LAD[3:0], LFRAME#, LRESET#, and LCLK, as well as the following optional LPC signals: SERIRQ, CLKRUN#, and LPCPD# (note that CLKRUN#, and LPCPD# signals share pins with GPIO, and should be properly selected to enable the respective function). The SST79LF008 flash memory can be read, written, erased and reprogrammed via LPC interface. The flash memory is divided into blocks and sectors that can be erased independently. Flash memory blocks can be protected to prevent accidental modification. All flash commands are interpreted by the device command interface. An on-chip memory controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected by the LPC Host software via flash memory status register. TABLE 7-1: Transfer Size Supported by the SST79LF008
Size of Transfer 1, 2, 4, 16, 128 bytes 1, 2, 4 bytes 1 byte 1 byte 1 byte 1 byte
T7-1.0 1320
Cycle Type Firmware Memory Read Firmware Memory Write LPC Memory Read LPC Memory Write I/O Read I/O Write
The LPC bus transfer uses four data signals LAD[3:0], one control signal LFRAME#, and LPC clock LCLK. Reset signal LRESET# will put the LPC interface module into a known reset state. The data signals, control signal and clock are designed to be compatible with PCI electrical specifications. The LPC interface operates with a clock speed of 33 MHz.
7.2 LPC Bus Cycles
The start of any LPC cycle is indicated by the LPC Host via active low LFRAME# signal. The START value for LPC cycle determines whether it is Firmware Memory or LPC Memory/LPC I/O cycle -- see Table 7-2 (the START value is the LAD[3:0] value latched on the last clock before the host chipset drives LFRAME# signal inactive from low-tohigh). TABLE 7-2: Firmware and LPC Memory Cycles START Field Definition
Definition Start of a LPC Memory Read/Write cycle or I/O Read/Write (next field specifies cycle type and direction) Start of a cycle for Firmware Memory Read Start of a cycle for Firmware Memory Write
T7-2.0 1320
7.1 LPC Bus Transfer
The SST79LF008 LPC interface implementation complies with LPC Interface Specification, Rev. 1.1, and always supports LPC I/O Read/Write cycle types. When LPCMODE bit of LPCMON register is `0', the SST79LF008 responds to Multi-Byte Firmware Memory Read/Write cycles on the LPC bus, and LPC Memory cycles are ignored. When LPCMODE bit of LPCMON register is `1', the SST79LF008 responds to Single-Byte LPC Memory Read/Write cycles on the LPC bus, and LPC Firmware Memory cycles are ignored. Table 7-1 summarize the size of transfers supported by the SST79LF008.
START Value 0000
1101 1110
See the following sections for detailed examples of Firmware Memory, LPC memory, and LPC I/O cycles. See Section 23 for the LPC related configuration options available in SST79LF008 device.
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Advance Information 7.2.1 Firmware Memory Cycles TABLE
Clock Cycle 1
7-3: Firmware Memory Read Cycle Field Definitions
Field Name START Field Contents1 1101 Direction LAD[3:0] IN Comments LFRAME# must be active (low) for the part to respond. Only the last start field (before LFRAME# transitioning high) should be recognized. The START field contents indicate a Firmware Memory Read cycle. Indicates which SST79LF008 device should respond. If the IDSEL (ID select) field matches the value specified by ID input pin, then that particular device will respond to the bus cycle. These seven clock cycles make up the 28-bit memory address. AAAA is one nibble of the entire address. Addresses are transferred most-significant nibble first. Indicates transfer size. Device will execute multi-byte read of 2YYYY bytes. SST79LF008 supports only YYYY = 0, 1, 2, 4, 7 (i.e., read 1, 2, 4, 16, 128 bytes). In this clock cycle, the host has driven the bus to all `1's and then floats the bus, prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The SST79LF008 takes control of the bus during this cycle. During this clock cycle, the SST79LF008 will generate a "ready-sync" (RSYNC) indicating that the least-significant nibble of the least-significant byte will be available during the next clock cycle. A = (13+2n+1); n = MSIZE Least significant nibbles outputs first. In this clock cycle, the SST79LF008 has driven the bus to all ones and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle". A = (13+2n+1); n = MSIZE The host resumes control of the bus during this cycle. A = (13+2n+1); n = MSIZE
T7-3.0 1320
2
IDSEL
0000 or 0001 AAAA
IN
3-9
MADDR
IN
10
MSIZE
YYYY
IN
11
TAR0
1111
IN, then Float Float, then OUT OUT
12 13
TAR1 RSYNC2
1111 (float) 0000
14-A (A+1)
DATA TAR0
DDDD 1111
OUT OUT, then Float Float, then IN
(A+2)
TAR1
1111 (float)
1. Field contents are valid on the rising edge of the present clock cycle 2. Between TAR1 and RSYNC cycles SST79LF008 may insert a number of "long- wait-sync" cycles (LWSYNC = 0110b), indicating that data is not ready, yet.
LCLK LFRAME#
Start IDSEL MADDR MSIZE TAR0 TAR1 RSYNC DATA Dn[3:0] Dn[7:4] TAR 1245 FirmMemRead.0
LAD[3:0]
1101b 0000b A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4]
A[3:0] YYYYb 1111b Tri-State 0000b D0[3:0] D0[7:4]
FIGURE
7-1: Firmware Memory Read Waveform
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Advance Information TABLE
Clock Cycle 1
7-4: Firmware Memory Write Cycle Field Definitions
Field Name START Field Contents1 1110 Direction LAD[3:0] IN Comments LFRAME# must be active (low) for the part to respond. Only the last start field (before LFRAME# transitioning high) should be recognized. The START field contents indicate a Firmware Memory Write cycle. Indicates which SST79LF008 device should respond. If the IDSEL (ID select) field matches the value specified by ID input pin, then that particular device will respond to the bus cycle. These seven clock cycles make up the 28-bit memory address. AAAA is one nibble of the entire address. Addresses are transferred most-significant nibble first. Indicates transfer size. Device will execute multi-byte write of 2YYYY bytes. SST79LF008 supports only YYYY = 0, 1, 2 (i.e., write 1, 2, 4 bytes. A = (10+2n+1); n = MSIZE Least significant nibble entered first. In this clock cycle, the master drives the bus to all `1's, and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle." A = (10+2n+1); n = MSIZE The SST79LF008 takes control of the bus during this cycle. A = (10+2n+1); n = MSIZE The SST79LF008 outputs the "ready-sync" value 0000b, indicating that it has received data or a flash command. A = (10+2n+1); n = MSIZE In this clock cycle, the SST79LF008 drives the bus to all `1's, and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle". A = (10+2n+1); n = MSIZE The host resumes control of the bus during this cycle. A = (10+2n+1); n = MSIZE
T7-4.0 1320
2
IDSEL
0000 or 0001 AAAA YYYY
IN
3-9 10
MADDR MSIZE
IN IN
11-A (A+1)
DATA TAR0
DDDD 1111
IN IN, then Float
(A+2) (A+3)
TAR1 RSYNC
1111 (float) Float, then OUT 0000 OUT
(A+4)
TAR0
1111
OUT, then Float
(A+5)
TAR1
1111 (float) Float, then IN
1. Field contents are valid on the rising edge of the present clock cycle
LCLK LFRAME#
Start IDSEL MADDR MSIZE A[3:0] YYYYb D0[3:0] D0[7:4] DATA TAR0 TAR1 RSYNC
LAD[3:0]
1110b 0000b A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4]
Dn[3:0] Dn[7:4] 1111b Tri-State 0000b TAR 1245 FirmMemWrite.0
FIGURE
7-2: Firmware Memory Write Waveform
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Advance Information 7.2.2 LPC Memory Cycles TABLE
Clock Cycle 1
7-5: LPC Memory Read Cycle Field Definitions
Field Name START Field Contents1 0000 Direction LAD[3:0] IN Comments Indicates start of a cycle. LFRAME# must be active (low) for the part to respond. Only the last start field (before LFRAME# transitioning high) should be recognized. Type of cycle and direction of transfer. Field contents indicates an LPC Memory Read cycle. Address Phase for Memory Cycle. LPC protocol supports a 32-bit address phase. AAAA is one nibble of the entire address. Addresses are transferred most-significant nibble first. The SST79LF008 encodes ID and register space access in the address fields. In this clock cycle, the host drives the bus to all `1's, and then floats the bus. This is the first part of the bus "turnaround cycle." The SST79LF008 takes control of the bus during this cycle. The SST79LF008 outputs the "ready-sync" value 0000b indicating that data will be available during the next clock cycle. This field is the least-significant nibble of the data byte. This field is the most-significant nibble of the data byte. In this clock cycle, the host drives the bus to all `1's, and then floats the bus. This is the first part of the bus "turnaround cycle." The host resumes control of the bus during this cycle.
T7-5.0 1320
2 3-10
CYCTYPE + DIR ADDR
010xb AAAA
IN IN
11 12 13 14 15 16 17
TAR0 TAR1 RSYNC2 DATA DATA TAR0 TAR1
1111 1111 (float) 0000 D3D2D1D0 D7D6D5D4 1111 1111 (float)
IN, then Float Float, then OUT OUT OUT OUT OUT, then Float Float, then IN
1. Field contents are valid on the rising edge of the present clock cycle 2. Between TAR1 and RSYNC cycles SST79LF008 may insert a number of "long- wait-sync" cycles (LWSYNC = 0110b), indicating that data is not ready, yet.
LCLK
LFRAME#
Start CYCTYPE + DIR 010Xb Address A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] Load Address in 8 Clocks A[11:8] A[7:4] A[3:0] TAR0 1111b TAR1 Tri-State Sync 0000b D[3:0] Data D[7:4] TAR
LAD[3:0]
0000b
1 Clock 1 Clock
2 Clocks
1 Clock Data Out 2 Clocks 1245 LPCMemRead.0
FIGURE
7-3: LPC Memory Read Cycle Waveform
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Advance Information TABLE
Clock Cycle 1
7-6: LPC Memory Write Cycle Field Definitions
Field Name START Field Contents1 0000 Direction LAD[3:0] IN Comments Indicates start of a cycle. LFRAME# must be active (low) for the part to respond. Only the last start field (before LFRAME# transitioning high) should be recognized. Type of cycle and direction of transfer. Field contents indicates an LPC Memory Write cycle. Address Phase for Memory Cycle. LPC protocol supports a 32-bit address phase. AAAA is one nibble of the entire address. Addresses are transferred most-significant nibble first. The SST79LF008 encodes ID and register space access in the address fields. This field is the least-significant nibble of the data byte. This field is the most-significant nibble of the data byte. In this clock cycle, the host drives the bus to all `1's, and then floats the bus. This is the first part of the bus "turnaround cycle." The SST79LF008 takes control of the bus during this cycle. The SST79LF008 outputs the "ready-sync" value 0000b indicating that it has received data or a flash command. In this clock cycle, the host drives the bus to all `1's and then floats the bus. This is the first part of the bus "turnaround cycle." The host resumes control of the bus during this cycle.
T7-6.0 1320
2 3-10
CYCTYPE + DIR ADDR
011xb AAAA
IN IN
11 12 13 14 15 16 17
DATA DATA TAR0 TAR1 RSYNC TAR0 TAR1
D3D2D1D0 D7D6D5D4 1111 1111 (float) 0000 1111 1111 (float)
IN IN IN, then Float Float, then OUT OUT OUT, then Float Float, then IN
1. Field contents are valid on the rising edge of the present clock cycle
LCLK
LFRAME#
Start CYCTYPE + DIR 011Xb Address A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] Load Address in 8 Clocks A[7:4] A[3:0] Data D[3:0] Data D[7:4] TAR0 TAR1 Sync 0000b 1 Clock 1245 LPCMemWrite.0 TAR
LAD[3:0]
0000b
1111b Tri-State 2 Clocks
1 Clock 1 Clock
Load Data in 2 Clocks
FIGURE
7-4: LPC Memory Write Cycle Waveform
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Advance Information 7.2.3 LPC I/O Cycles TABLE
Clock Cycle 1
7-7: LPC I/O Read Cycle Field Definitions
Field Name START Field Contents1 0000 Direction LAD[3:0] IN Comments Indicates start of a cycle. LFRAME# must be active (low) for the part to respond. Only the last start field (before LFRAME# transitioning high) should be recognized. Type of cycle and direction of transfer. Field contents indicates an LPC I/O Read cycle. Address Phase for Memory Cycle. LPC protocol supports a 16-bit address phase. AAAA is one nibble of the entire address. Addresses are transferred most-significant nibble first. In this clock cycle, the host drives the bus to all `1's, and then floats the bus. This is the first part of the bus "turnaround cycle." The SST79LF008 takes control of the bus during this cycle. The SST79LF008 outputs the "ready-sync" value 0000b indicating that data will be available during the next clock cycle. This field is the least-significant nibble of the data byte. This field is the most-significant nibble of the data byte. In this clock cycle, the host drives the bus to all `1's and then floats the bus. This is the first part of the bus "turnaround cycle." The host resumes control of the bus during this cycle.
T7-7.0 1320
2 3-6
CYCTYPE + DIR ADDR
000xb AAAA
IN IN
7 8 9 10 11 12 13
TAR0 TAR1 RSYNC DATA DATA TAR0 TAR1
1111 1111 (float) 0000 D3D2D1D0 D7D6D5D4 1111 1111 (float)
IN, then Float Float, then OUT OUT OUT OUT OUT, then Float Float, then IN
1. Field contents are valid on the rising edge of the present clock cycle
LCLK
LFRAME#
Start CYCTYPE + DIR 000Xb A[15:12] Address A[11:8] A[7:4] A[3:0] TAR0 1111b TAR1 Tri-State Sync 0000b D[3:0] Data D[7:4] TAR
LAD[3:0]
0000b
1 Clock 1 Clock
Load Address in 4 Clocks
2 Clocks
1 Clock Data Out 2 Clocks
1245 LPC_IO_Read.0
FIGURE
7-5: LPC I/O Read Cycle Waveform
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Advance Information TABLE
Clock Cycle 1
7-8: LPC I/O Write Cycle Field Definitions
Field Name START Field Contents1 0000 Direction LAD[3:0] IN Comments Indicates start of a cycle. LFRAME# must be active (low) for the part to respond. Only the last start field (before LFRAME# transitioning high) should be recognized. Type of cycle and direction of transfer. Field contents indicates an LPC I/O Write cycle. Address Phase for Memory Cycle. LPC protocol supports a 16-bit address phase. AAAA is one nibble of the entire address. Addresses are transferred most-significant nibble first. This field is the least-significant nibble of the data byte. This field is the most-significant nibble of the data byte. In this clock cycle, the host drives the bus to all `1's, and then floats the bus. This is the first part of the bus "turnaround cycle." The SST79LF008 takes control of the bus during this cycle. The SST79LF008 outputs the "ready-sync" value 0000b indicating that it has received data. In this clock cycle, the host drives the bus to all `1's, and then floats the bus. This is the first part of the bus "turnaround cycle." The host resumes control of the bus during this cycle.
T7-8.0 1320
2 3-6
CYCTYPE + DIR ADDR
001xb AAAA
IN IN
7 8 9 10 11 12 13
DATA DATA TAR0 TAR1 RSYNC TAR0 TAR1
D3D2D1D0 D7D6D5D4 1111 1111 (float) 0000 1111 1111 (float)
IN IN IN, then Float Float, then OUT OUT OUT, then Float Float, then IN
1. Field contents are valid on the rising edge of the present clock cycle
LCLK
LFRAME#
Start CYCTYPE + DIR 001xb A[15:12] Address A[11:8] A[7:4] A[3:0] Data D[3:0] Data D[7:4] TAR0 TAR1 Sync 0000b 1 Clock 1245 LPC_IO_Write.0 TAR
LAD[3:0]
0000b
1111b Tri-State 2 Clocks
1 Clock 1 Clock
Load Address in 4 Clocks
Load Data in 2 Clocks
FIGURE
7-6: LPC I/O Write Cycle Waveform
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Advance Information
7.3 LPC Flash Command Definitions
All memory write operations are interpreted by the LPC Flash command interface. Commands consist of one or more sequential bus write operations. After power-up or reset, the device enters into the read array mode. For TABLE 7-9: LPC Flash Command Definitions1
Bus Cycles Required 1 2 2 1 2 2 2 1 1 2 2 2 2 2 First Bus Cycle Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr X X X X X X X X X X X X X X Data FFH 90H 70H 50H 30H 20H 40H or 10H B0H D0H A5H 85H 60H 65H 6AH Write Write Write Write Write WA X X X X WD 00H 76H 8AH 79H
T7-9.0
power-up and reset details, see Section 5.2. The commands are summarized in Table 7-9. For detail of each command, refer to the sections below.
Second Bus Cycle Oper Read Read Write Write Write Addr IA X SA BA WA Data ID SRD D0H D0H WD Notes 2,3 3 4 4 4
Command Read Array/Reset Read Device ID Read Unique ID Read Status Register Clear Status Register Sector Erase Block Erase Program Erase Suspend Erase Resume User Unique ID Program User Unique ID Program Lockout Enter UNVR(3K OTP) / Enter ENVR Force LPC Soft Reset Release LPC Soft Reset
5 6 7 7
1320
1. X = Any valid address within the device main flash memory array address space (FFF0 0000H to FFFF FFFFH). IA = Device Identification (ID) address/Unique ID address SA/BA = Address of sector or block being erased (any valid address within the respective sector/block) WA = Address of memory location to be written to SRD = Data read from Status Register WD = Data written to address WA ID = Data read from Device identifier codes or Unique ID 2. Read operations, following the Read Device/Unique ID command, access either Manufacturer ID, or Device ID, or Unique ID. Valid Manufacturer and Device ID addresses are FFFC 0000H and FFFC 0001H, respectively. Valid address range for SST Pre-Programmed 8-byte Factory Unique ID is from FFFC 0180H to FFFC 0187H. Valid address range for User Programmable 24-byte Unique ID is from FFFC 0188H to FFFC 019FH. 3. Subsequent reads continue to return ID or Status data until another valid command is issued. 4. The sector or block to be erased or programmed must not be write-locked, otherwise the operation will fail. 5. Valid User Programmable Unique ID addresses are from FFFC 0188H to FFFC 019FH. 6. After enter ENVR/UNVR command is executed Valid address for 4K ENVR area is from FFF0 0000H to FFF0 0FFFH. Valid address for 3K OTP UNVR area is from FFF0 1000H to FFF0 1BFFH. 7. These 2 commands are not standard flash memory control commands. Do not use these commands unless the KBC firmware and BIOS are corrupted.
Two LPC write cycles within 2-cycle command must be consecutive. The command sequence has to be restarted from the first cycle, if the second cycle data is incorrect, the second cycle is a read from memory array, or the second cycle is a read/write access to LPC memory mapped registers. For more information on LPC memory mapped registers, see Section 7.6. However, if the second cycle is aborted or contains invalid fields, it will be ignored, and the command sequence does not need to be restarted. See Section 7.4 for LPC abort mechanisms and invalid fields.
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All address ranges defined for LPC flash commands are specified as 32-bit system memory addresses, and are valid when SST79LF008 is used as a boot firmware memory device (low level is applied to ID input pin). When the SST79LF008 is not a boot device, the respective addresses will be changed according to Multiple Device Selection mechanism described in Section 7.5.
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Advance Information 7.3.1 Read Array Command After Power-On, Brown-Out, External, WDT, or aLPC Soft Reset, the device defaults to the read array mode. The read operation can also be initiated by issuing the Read Array/Reset Command. The device remains available for main flash memory array reads until another command is written. Once an internal Program/Erase operation starts, the device will not recognize the Read Array/Reset command until the operation is completed, unless the erase operation is suspended via an Erase Suspend command as described in Section 7.3.7. 7.3.2 Read Device Identifier Command The Read ID operation is initiated by writing the Read Device ID command. Following the write of this command, the device outputs the manufacturer and device ID data from the addresses shown in Table 7-10. Write any other valid command to the device to terminate the Read ID operation. 7.3.3.1 Flash Memory Status Register
7 Name Reset Bit 7 WSMS 1 Description Write State Machine Status Check WSMS to determine erase or program completion. 1 = Ready 0 = Busy Erase Suspend Status 1 = Erase Suspended 0 = Erase in progress/completed Block Protect Status The Block Write-Lock bit is interrogated only after erase or program command is issued. It informs the system whether or not the selected block is locked. This bit does not provide a continuous indication of write-lock bit value. 1 = Write-lock bit is set (operation aborted) 0 = Block is unlocked Reserved for future use
T7-10.0 1320
.
TABLE 7-10: Product Identification
Address Manufacturer's ID (SST) Device ID (SST79LF008) FFFC 0000H FFFC 0001H Data BFH F0H
T7-10.0 1320
7.3.3 Read Status Register Command The Status register provides information on the current or previous Program or Erase operation. The Status register may be read to determine when a program or sector/block erase command completes, and whether the operation completed successfully. The Status register may be read at any time by issuing the Read Status Register Command. After writing this command, all subsequent read operations within the device main flash memory array will return the data from the status register until another valid command is written. The Status Register bits are summarized in Register 7.3.3.1.
6 ESS 0
5 0
4 0
3 0
2 0
1 BPS 0
0 0
6
1
5:2, 0
7.3.4 Clear Status Register Command The Clear Status Register command can be used to reset the BPS bit in the Status register to `0'. This bit does not automatically return to `0' when a new Program or Erase command is issued. Therefore, it should be cleared by issuing the Clear Status Register Command before attempting a new Program or Erase command. Device Power-On, Brown-Out, External, WDT, or aLPC Soft Reset will return Status Register to its reset value, and clear BPS to `0'.
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Advance Information 7.3.5 Sector Erase Command and Block Erase Command The Erase Command operates on one sector or block at a time. This command requires an arbitrary address within the targeted sector or block (SA or BA) to be specified in the second bus cycle. Note that a Sector/Block Erase operation changes all Sector/Block byte data to FFH. If a read operation is performed within the main flash memory array after issuing the erase command, the device will automatically output Status Register data. The system can poll the Status Register in order to verify the completion of the Sector/Block Erase operation. If a Sector/Block Erase is attempted on a locked block, the operation will fail and the data in the Sector/Block will not be changed. In this case, the Status Register will report the error (BPS = 1). During the Block Erase or Sector Erase operation, the device will only accept the Read Status Register or the Erase Suspend commands. All other commands will be ignored until the operation is completed. 7.3.6 Program Command The Program Command writes data (WD) specified in the second bus cycle to the consecutive flash memory locations starting with the specified address (WA). The data size can be specified as 1, 2, or 4 bytes for Firmware Memory cycles, and 1 byte only for LPC memory cycles. After issuing Program command the device automatically outputs the Status Register data when read within the main flash memory array. The system can poll the Status Register in order to verify the completion of the Program operation. If a Program operation is attempted on a locked block, the operation will fail and the data in the addressed byte will not be changed. In this case, the Status Register will report the error (BPS = 1). During the Program operation, the device will only accept the Read Status Register command. All other commands will be ignored until the operation is completed. 7.3.7 Erase Suspend Command and Erase Resume Commands The Erase Suspend command allows Sector or Block Erase interruption in order to read or program data in another block of memory. Once the Erase Suspend command is executed, the device will suspend any in-progress Erase operation within time TES. See Table 24-8. The device outputs status register data, when read within the main flash memory array, after the Erase Suspend command is written. After erase operation is actually suspended, the device will set the Status Register bit ESS = 1. Thus, the system can determine whether the erase operation has been suspended (WSMS = 1 and ESS = 1) or completed (WSMS = 1 and ES = 0) by polling the Status Register. After a successful suspend, a Read Memory Array command may be issued to read data from a block other than the suspended block. A Program command may also be issued while Erase is suspended to program data in memory locations other than the sector or block currently in the Erase Suspend mode. If a Read Array command is written to an address within the suspended Sector/Block, this may result in reading invalid data. If a Program command is written to an address within the suspended Sector/Block, the command is acknowledged but ignored. Other valid commands while an erase is suspended include Read Status Register, Read Device ID, and Erase Resume. The Erase Resume command resumes the erase operation in the suspended sector or block. After the Erase Resume command is written, the device will continue the erase operation. Erase cannot resume until any program operations initiated during erase suspend have completed. Suspended operations cannot be nested. That is, the system needs to complete/resume any previously suspended operation before a new operation can be suspended. Once the Erase Resume command is issued, the subsequent bus read operations within the main flash memory array read the status register. 7.3.8 User Unique ID Read, Program and Lockout Commands The 256-bits (32 bytes) of the SST79LF008 Unique ID space are divided into two segments. One 64-bit segment is programmed at SST with a unique 64-bit number, which is unchangeable. The other 192-bit segment is a one time programmable segment (OTP) which is left blank for customers to program as desired. Once the customer segment is programmed, it can be locked to prevent reprogramming. Note that regardless of whether or not the Unique ID is locked, neither of the Unique ID segments can be erased. In order to read the Unique ID information, the user can issue a Read Unique ID command to the device. At this point the device enters the Read Device/Unique ID mode. The Unique ID information can be read at the following memory addresses (IA): * * FFFC 0180H to FFFC 0187H - SST Factory PreProgrammed ID (8 bytes - 64 bit). FFFC 0188H to FFFC 019FH - User Programmed Unique ID (24 bytes - 192bit).
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Advance Information A Read Array/Reset command must then be issued to the device in order to exit the "Read Device/Unique ID" mode and return to read array mode. An alternative method to read the Unique ID information without switching from read array mode is to read the respective registers located in the firmware flash memory register space described in Section 7.6. In this case the Unique ID information can be retrieved in read array mode at the following register addresses: * * FFBC 0180H to FFBC 0187H - SST Pre-Programmed Device ID Segment (8 bytes - 64bit). FFBC 0188H to FFBC 019FH - User Programmed Unique ID Segment (24bytes - 192bit).
7.4 LPC Abort Mechanism and Invalid Fields
If LFRAME# is driven low for one or more clock cycles after the start of a bus cycle, the cycle will be terminated. The host may drive the LAD[3:0] with 1111b (ABORT nibble) to return the interface to ready mode. The ABORT only affects the current bus cycle. For a multi-cycle command sequence, such as the Erase or Program commands, ABORT doesn't interrupt the entire command sequence, only the current bus cycle of the command sequence. The host can re-send the bus cycle for the aborted command and continue the command sequence after the device is ready again. During an on-going LPC bus cycle, the SST79LF008 will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is explained in Sections 7.4.1 and 7.4.2. 7.4.1 Response to Invalid Fields for Firmware Memory Cycle ID mismatch: The SST79LF008 compares ID bits in the IDSEL field with the ID value specified by the SST79LF008 input ID pin. If there is a mismatch, the device will ignore the cycle. See Multiple Device Selection, Section 7.5 for details. Address out of range: The address sequence is 7 fields long (28 bits) for Firmware Memory bus cycles. Only address bits A0 to A19 and A22 are decoded by the SST79LF008. Address A22 has the special function of directing reads and writes to the flash core (A22 = 1) or to the register space (A22 = 0). Invalid MSIZE field: If the SST79LF008 receives an invalid size field during a Firmware Memory Read or Write operation, the device will ignore the cycle and no operation will be attempted. The device will not generate any kind of response in this situation. The SST79LF008 will only respond to MSIZE values listed in the Table 7-11. TABLE 7-11: Valid MSIZE Field for Firmware Memory Cycle
Bits 0000 0001 0010 0100 0111 Direction R/W R/W R/W R R Size of transfer 1 Byte 2 Byte 4 Byte 16 Byte 128 Byte
T7-11.0 1320
In order to Program the Unique ID, a Program Unique ID command should be issued with the address (WA) in the range of FFFC 0188H to FFFC 019FH. Processing of this command is similar to the main flash array program command described above. In order to protect Unique ID from corruption, Unique ID Program Lockout command should be used. 7.3.9 Enter UNVR (3K OTP) / Enter ENVR Commands The Enter UNVR/ENVR access mode command is used to access 3 KByte OTP UNVR and 4 KByte flash ENVR. Once the Enter UNVR/Enter ENVR command is issued, the LPC Host can read ENVR information at addresses FFF0 0000H to FFF0 0FFFH in LPC address space and read UNVR at addresses FFF0 1000H to FFF0 1BFFH in LPC address space. The LPC Host can also erase/program ENVR as well as program UNVR using the same Sector Erase and Program commands as for the main flash array. A Read Array/Reset command must be issued to the device in order to exit the UNVR/ENVR access mode and return to read main flash array mode. 7.3.10 Force / Release LPC Soft Reset Commands The Force LPC Soft Reset command is used to put 8051 into LPC Soft Reset state and unconditionally release the flash memory bus to the LPC Host. This command aborts KBC operation, and it is not recommended, unless KBC firmware and BIOS code are both corrupted. The Release LPC Soft Reset command is used to restart 8051 code execution and KBC operations after LPC Soft reset. Note. In addition to Release command, the LPC Soft Reset state is also terminated by Power-On, Brown-Out, External, WDT or aLPC Soft Reset, as well as by LPC Interface Reset (LRESET#) and LPC Power Down (LPCPD#) signals.
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Advance Information Once valid START, IDSEL, and MSIZE are received, the SST79LF008 will always complete the bus cycle. However, if the device is busy performing a flash Erase or Program operation, no new internal memory write will be executed. As long as the states of LAD[3:0] and LFRAME# are known, the response of the SST79LF008 to signals received during the cycle is predictable. Non-boundary-aligned address: The SST79LF008 accepts Multi-Byte transfers for both Read and Write operations. The device address space is thus divided into pages of uniform size 2, 4, 16, or 128 Byte wide, according to the MSIZE value. The host issues only one address in the MADDR field of the Firmware Memory Cycle but multiple bytes are read from, or written to, the device. For this reason the MADDR address should be page "boundary aligned". Boundary aligned means that for a 2 Byte transfer the address should be aligned to a Word boundary (A0 = 0), for a 4 Byte transfer the address should be aligned to a Double Word boundary (A0 = 0, A1 = 0), etc. If the address supplied by the host is not page "boundary aligned", the SST79LF008 will force a boundary alignment, starting the Multi-Byte Read or Write operation from the lower Byte of the addressed page. 7.4.2 Response to Invalid Fields for LPC Memory Cycle ID mismatch: The SST79LF008 interprets address bits [A24:A23, A21:A20] as ID information and compares them with the complement of ID value specified by the SST79LF008 input ID pin. If there is a mismatch, the device will ignore the cycle. See Multiple Device Selection, Section 7.5, for details. Address out of range: The address sequence is 8 fields long (32 bits). The address bits [A24:A23, A21:A20] for the SST79LF008 are used to select the device with proper IDs. The most significant address bits [A31:A25] must be "1's" for LPC memory cycle to be completed. Address A22 has the special function of directing reads and writes to the flash core (A22 = 1) or to the register space (A22 = 0). For the boot device (with LPC protocol ID = 0), the SST79LF008 also decodes the physical addresses of the top 128 KByte blocks at two system memory ranges: * * FFFF FFFFH to FFFE 0000H--top of 4 GByte address space 000F FFFFH to 000E 0000H--top of legacy 1 MByte address space forming a flash Erase or Program operation, no new internal memory write will be executed. As long as the states of LAD[3:0] and LFRAME# are known, the response of the SST79LF008 to signals received during the LPC cycle is predictable.
7.5 Multiple Device Selection
Multiple LPC firmware memory devices may be strapped to increase memory densities in a system. BIOS support, bus loading, or the attaching bridge may limit the number of connected devices. The boot device must respond to LPC protocol with ID of 0 (0000b); subsequent devices use incremental numbering. Equal density must be used with multiple devices. With one ID input pin SST79LF008 can have two different LPC protocol ID values. Respectively, SST79LF008 flash memory array will be mapped into two different address ranges in the 4GByte system memory space depending on ID pin logic level. When VIL level is applied to ID input pin, the valid LPC protocol ID is 0 (0000b). When VIH level is applied to ID input pin, the valid LPC protocol ID is 1 (0001b). 7.5.1 Multiple Device Selection for Firmware Memory Cycle For Firmware Memory Read/Write cycles, LPC protocol ID information is included into IDSEL field of every cycle. The ID value specified by SST79LF008 ID input pin (0000b or 0001b) must match the value in IDSEL field. If there is a mismatch the SST79LF008 will ignore the respective LPC Firmware Memory cycle. 7.5.2 Multiple Device Selection for LPC Memory Cycle For LPC Memory Read/Write cycles, LPC protocol ID information is included in the address bits of every cycle. The address bits [A24:A23, A21:A20] are used to select the device with proper IDs. The ID bits in the address field must match the inverse of the ID value specified by SST79LF008 ID input pin (i.e., address bits should be 1111b when VIL level is applied to ID input pin or 1110b when VIH level is applied to ID input pin). If there is a mismatch the SST79LF008 will ignore the respective LPC Memory cycle.
Once valid START, CYCTYPE + DIR, and address range, including ID bits, are received, the SST79LF008 will always complete the bus cycle. However, if the device is busy per(c)2006 Silicon Storage Technology, Inc. S71320-01-000 10/06
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Advance Information
7.6 LPC Memory Mapped Registers.
The LPC memory mapped registers can be accessed by LPC Firmware Memory cycles as well as by LPC Memory cycles with address bit A22 = 0. Four types of registers are implemented in SST79LF008: Block Locking registers, JEDEC ID Registers, Multi-byte Read/Write Configuration Registers, and Unique ID Registers. These registers appear at their respective addresses in the 4GByte system memory address space as specified in Table 7-12 for the boot device. They will appear elsewhere if SST79LF008 is not the boot device according to Multiple Device Selection TABLE 7-12: Block Locking Registers
Protected Memory Register T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK T_MINUS08_LK T_MINUS09_LK T_MINUS10_LK T_MINUS11_LK T_MINUS12_LK T_MINUS13_LK T_MINUS14_LK T_MINUS15_LK T_MINUS16_LK T_MINUS17_LK T_MINUS18_LK Size 16K 8K 8K 32K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K Address Range 0FFFFFH-0FC000H 0FBFFFH-0FA000H 0F9FFFH-0F8000H 0F7FFFH-0F0000H 0EFFFFH-0E0000H 0DFFFFH-0D0000H 0CFFFFH-0C0000H 0BFFFFH-0B0000H 0AFFFFH-0A0000H 09FFFFH-090000H 08FFFFH-080000H 07FFFFH-070000H 06FFFFH-060000H 05FFFFH-050000H 04FFFFH-040000H 03FFFFH-030000H 02FFFFH-020000H 01FFFFH-010000H 00FFFFH-000000H
mechanism described in Section 7.5. Read access to unused register locations will return 00H. Write access to these locations has no effect. Attempts to read or write any register during internal Program/Erase operation are completed normally. 7.6.1 Flash Memory Block Locking Registers SST79LF008 provides software controlled lock protection through a set of Block Locking registers. These registers are read/write accessible via standard memory locations specified in Table 7-12.
Memory Map Register Address for Boot Device FFBFC002H FFBFA002H FFBF8002H FFBF0002H FFBE0002H FFBD0002H FFBC0002H FFBB0002H FFBA0002H FFB90002H FFB80002H FFB70002H FFB60002H FFB50002H FFB40002H FFB30002H FFB20002H FFB10002H FFB00002H
Reset Value1 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
T7-12.0 1320
1. All block locking registers returned to their reset values specified above after any one of the following reset events: Power-On Reset, External Reset, Watchdog Timer Reset, Brown-Out Reset, aLPC Soft Reset, or external LPC Interface Reset (see also Section 5.2.)
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Advance Information In case of multi-byte register reads with Firmware Memory cycle, the device will return register data for the addressed register until the command finishes or is aborted. TABLE 7-13: Block Locking Register Bits
Reserved Bit [7:3] 00000 00000 00000 00000 00000 00000 00000 00000 Read-Lock Bit [2]1 0 0 0 0 1 1 1 1 Lock-Down Bit [1] 2 0 0 1 1 0 0 1 1 Write-Lock Bit [0] 3 0 1 0 1 0 1 0 1 Lock Status Full Access Write Locked (Default State after reset) Locked Open (Full Access Locked Down) Write Locked Down Block Read Locked (Registers alterable) Block Read & Write Lock (Registers not alterable) Block Read Locked Down (Register not alterable) Block Read & Write lock Down (Register not alterable)
T7-13.0 1320
Bit definitions for block locking registers are specified in Table 7-13.
1. Read Lock: The Read-Lock bit, bit 2, controls the read access. The default read status of all blocks after reset is read-unlocked. When a block's read lock bit is set, data cannot be read from that block. An attempted read from a read-locked block will result in the data 00h. The read lock status can be unlocked by clearing the read lock bit, provided that the block is not locked down. The current read lock status of a particular block can be determined by reading the corresponding read-lock bit. 2. Lock Down. The Lock-Down bit, bit 1, controls the Block Locking register. The default Lock Down status of all blocks after reset is not locked down. Once the Lock-Down bit is set, any future attempted changes to that Block Locking register will be ignored. The LockDown bit is only cleared upon a device reset. Current Lock Down status of a particular block can be determined by reading the corresponding Lock-Down bit. Once a block's Lock-Down bit is set, the Read- and Write-Lock bits for that block can no longer be modified, and the block is locked down in its current state of read/write accessibility. 3. Write-Lock: The Write-Lock bit, bit 0, controls the Program/Erase lock state. The default Write status of all blocks after reset is write locked. When bit 0 of the Block Locking register is set, Program and Erase operations for the corresponding block is prevented. Clearing the Write-Lock bit will unprotect the block. The Write-Lock bit must be cleared prior to starting a Program or Erase operation because it is sampled at the beginning of the operation.
Note: The registers (T_BLOCK_LK, T_MINUS01_LK, T_MINUS02_LK, and T_MINUS03_LK) protect memory areas within one 64 KByte flash memory Block15 (see Figure 4-1). Therefore, when any of these memory areas are writeprotected the Block Erase command for Block15 is not accepted. 7.6.2 JEDEC ID Registers The JEDEC ID registers are read-only registers and are accessible via memory locations specified in Table 7-14. In case of multi-byte register reads with Firmware Memory cycle, the device will return register data for the addressed register until the command finishes or is aborted. TABLE 7-14: JEDEC ID Registers
Register Address for Boot Device FFBC0000H FFBC0001H
7.6.3 Multi-byte Read/Write Configuration Registers The multi-byte read/write configuration (MBR) registers are four 8-bit read-only registers located at addresses specified in Table 7-15. These registers are accessible using Firmware Memory Read cycle only. The device will return unused register space data (00H) if these registers are addressed via LPC memory read cycles. These registers contain information about multi-byte read and write access sizes that will be accepted for Firmware Memory multi-byte commands. In case of multi-byte register reads, device will return register data for addressed register until the command finishes or is aborted.
Register Manufacturer ID Device ID (SST79LF008)
Value BFH F0H
Access R R
T7-14.0 1320
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Advance Information TABLE 7-15: Multi-byte Read/Write Configuration registers
Register Address for Boot Device FFBC0005H FFBC0006H FFBC0007H FFBC0008H
Register MULTI_BYTE_READ_L MULTI_BYTE_READ_H MULTI_BYTE_WRITE_L MULTI_BYTE_WRITE_H
Value 0100 1011b 0000 0000b 0000 0011b 0000 0000b
Access R R R R
Description Device supports 1,2,4, 16, 128 byte reads Future Expansion for read Device supports 2,4 byte write Future Expansion for write
T7-15.0 1320
7.6.4 Unique ID Registers In addition to Read Unique ID command described in Section 7.3, the SST79LF008 allows the LPC Host to read Unique ID Information and its Write Lock/Unlock status via LPC memory mapped register space at addresses defined in Table 7-16. In case of multi-byte register reads with Firmware Memory cycle, for the all UID_BYTE registers, the device will return page aligned sequential register data with TABLE 7-16: Unique ID Registers
Register UID_WRITE_LOCK UID_BYTE_0 UID_BYTE_1 UID_BYTE_2 UID_BYTE_3 UID_BYTE_4 UID_BYTE_5 UID_BYTE_6 UID_BYTE_7 UID_BYTE_8 UID_BYTE_9 ... UID_BYTE_30 UID_BYTE_31 Register Address FFBC017FH FFBC0180H FFBC0181H FFBC0182H FFBC0183H FFBC0184H FFBC0185H FFBC0186H FFBC0187H FFBC0188H FFBC0189H ... FFBC019EH FFBC019FH
wrap-around until the command finishes or is aborted. Multi-byte read of UID_WRITE_LOCK register will return register data for the addressed register until the command finishes or is aborted. All Unique ID registers are read-only registers. The Unique ID Program and Lockout commands shown in Table 7-16 can be used to write (program) and lock Unique ID.
Value 0000 0000b 0000 0001b R R R R R R R R R R R
Access
Description Write Unlocked Write Locked Factory Programmed Factory Programmed Factory Programmed Factory Programmed Factory Programmed Factory Programmed Factory Programmed Factory Programmed User Programmed User Programmed ... User Programmed User Programmed
T7-16.0 1320
... R R
7.7 PCI CLOCK RUN CONTROL SUPPORT
The SST79LF008 supports the CLKRUN# input/open drain output signal according to the PCI Mobile Design Guide Rev 1.0 specification. This signal is used by the system to indicate the LPC clock status. When CLKRUN# is "high", the LPC clock is, or is about to be, stopped. When CLKRUN# is "low", the LPC clock is running. The CLKRUN# is used by SST79LF008 to request restarting the stopped clock in order to report the Serialized IRQs status changes. If any module within the SST79LF008 asserts or de-asserts serialized interrupt to the system and the CLKRUN# input is "high", the SST79LF008 can request the restoration of the clock by the assertion of the CLKRUN# signal low. The SST79LF008 drives CLKRUN#
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Advance Information low until it detects two rising edges of the restarted LPC clock. After the second clock edge, the SST79LF008 disables its CLKRUN# open drain driver. The SST79LF008 would not assert CLKRUN# if it is already driven low by the central resource or any other device on the bus. Also, the SST79LF008 would not assert CLKRUN# unless the line has been de-asserted for two successive clocks; for example, before the clock was stopped. Additionally, CLKRUN# is asserted if 8051 core tries to access any device 0, 1, or 3 configuration register and the device configuration register index 30H value is 00H (inactive). See Table 23-1 for Configuration Registers Map. Refer to the PCI Mobile Design Guide Rev 1.0 for a detailed description of the CLKRUN# function.
7.8 LPC Power Down Protocol Support
The SST79LF008 supports the LPCPD# input signal. This signal is asserted by the system prior to going to low-power state. After LPCPD# is activated (with at least 30 microseconds delay) the LPC clock is stopped low, and the other host LPC I/F output signals being tri-stated or driven low. Upon recognizing that LPCPD# is asserted, there will be no further transactions on the LPC interface. While LPCPD# is asserted, the SST79LF008 continues to drive IRQ1 and IRQ12 frames. After LPCPD# is de-asserted, the LPC interface may be reset depending on the characteristics of the system reset signal connected to LRESET# pin. The SST79LF008, however, resets internal LPC protocol state machine on exit from LPC low power state without LRESET# going active. The SST79LF008 asynchronously recognizes LPCPD# state changes from active to inactive and vice versa. (Note that LPCPD# signal, may not meet setup times to LCLK, however, it can be sampled with LCLK, since the clock is running for at least 30 microseconds after LPCPD# goes low, and for more than 30 microseconds prior to LPCPD# going high.) The state of the LPCPD# signal can be directly read via LPCMON register (see Section 23.1); LPCPD# signal transition generates interrupt request to 8051 core via WSRCG register (see Section 8.3). Refer to the LPC Interface Specification, Rev 1.1 for a detailed description of the LPCPD# function.
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Advance Information
8.0 INTERRUPTS AND WAKEUPS 8.1 SST79LF008 Interrupts
SST79LF008 has eleven interrupt sources under a fourlevel priority scheme. Table 8-1 and Figures 8-1, 8-2, 8-3, 8-4, and 8-5 summarize the supported interrupt structure. Interrupt 0 (INT0) is dedicated for matrix keyboard event. Interrupt 1 (INT1) combines interrupt source registers A and B. Interrupt 2 (INT2) combines wakeup event source registers A and B. Interrupt 3 (INT3) combines wakeup event source registers C,D, and E. Interrupt 4 (INT4) combines wakeup event source registers F,G, H and I. Interrupt 5 (INT5) combines wakeup event source registers J, K, L, M, N, O and P For details on INT0-INT5 interrupt sources . see Section 8.3. Timer 0 and Timer 1 (TF0, TF1) as well as serial interface interrupt (SPI) are dedicated interrupts. Timer 2 interrupt combines timer 2 overflow and external flag interrupts (TF2 or EXF2). Serial port UART interrupt combines transmit and receive interrupts (TI or RI). For details on Timer 0-2, UART and SPI interrupt sources see Sections 10.0, 11.0, 12.0.
TABLE
8-1: SST79LF008 Interrupt Sources
Priority within level1 1 2 3 4 5 6 7 8 9 10 11 Interrupt request flag TCON.1 TCON.5 TCON.3 TCON.7 SCON.0(RI), SCON.1(TI) T2CON.7(TF2), T2CON.6(EXF2) EXIF.0 EXIF.1 EXIF.2 EXIF.3 SPSR.7 Priority level control IP.0,IPH.0 IP.1,IPH.1 IP.2,IPH.2 IP.3,IPH.3 IP.4,IPH.4 IP.5,IPH.5 IPA.0,IPAH.0 IPA.1,IPAH.1 IPA.2,IPAH.2 IPA.3,IPAH.3 IP.7,IPH.7 Interrupt vector address 03H 0BH 13H 1BH 23H 2BH 33H 3BH 43H 4BH 53H Wakeup Idle/Power Down Yes/Yes Yes/No Yes/No Yes/No Yes/No Yes/No Yes/Yes Yes/Yes Yes/Yes Yes/Yes Yes/Yes
T8-1.1320
Interrupt INT0 TF0 INT1 TF1 TI or RI TF2 or EXF2 INT2 INT3 INT4 INT5 SPI
Description Keyboard Timer 0 interrupt Interrupt source A and B Timer 1 interrupt UART Timer 2 interrupt External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 SPI interrupt
ENABLE IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 IEA.0 IEA.1 IEA.2 IEA.3 SPCR.7
1. Priority within level order -- 1(INTO)=highest/11(SPI)=lowest--is used to resolve simultaneous interrupt requests of the same level.
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Advance Information
"1" KSI0
D
Q
KEYCLEAR#
KEY(KEYWSRC.0) KEYBOARD
"1" KSI7
D
Q
KEYCLEAR#
KEYMSK (KEYWSRC.1)
CHIP LOGIC RESET KEYCLEAR# WRITE 0 TO KEY(KEYWSRC.0) PULSE GENERATOR
0 1 2 3 4 5 6
WDT CLKINT ADCINT RESERVED SM0INT SM1INT KCIBF
0 1 2 3 4 5 6
WDTMSK CLKINTMSK ADCINTMSK RESERVED SM0INTMSK SM1INTMSK KCIBFMSK
7 KCOBE Interrupt Source A Register 0 1 2 3 4 5 6 PS20INT PS21INT PS22INT ECIBF1 ECOBE1 MBXINT ECIBF
7 KCOBEMSK Interrupt Source A Mask Register 0 1 2 3 4 5 6 PS20INTMSK PS21INTMSK PS22INTMSK ECIBF1MSK ECOBE1MSK MBXINTMSK ECIBFMSK
INT1
7 ECOBE Interrupt Source B Register 0 1 2 3 4 5 6 LPC HIB RESERVED SPICLK PS2 SBO PS2 SB1 PS2 SB2
7 ECOBEMSK Interrupt Source B Mask Register 0 1 2 3 4 5 6 LPCMSK HIBMSK RESERVED SPICLKMSK PS2 SBOMSK PS2 SB1MSK PS2 SB2MSK
7 SM0 DATA Wakeup Source A Register 0 1 2 3 4 5 6 SM1 DATA SM2 DATA ALPCINT LRESET RESERVED RESERVED FAN1
7 SM0 DATAMSK Wakeup Source A Mask Register 0 1 2 3 4 5 6 SM1 DATAMSK SM2 DATAMSK ALPCINTMSK LRESETMSK RESERVED RESERVED FAN1MSK
INT2
7 FAN2 Wakeup Source B Register
FAN2MSK 7 Wakeup Source B Mask Register
1245 IntSturcture0.1.0
FIGURE
8-1: SST79LF008 Interrupt Structure (int1-int2)
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GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7
0 1 2 3 4 5 6 7
Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F)
0 1 2 3 4 5 6 7
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 Wakeup Source C Register
0 1 2 3 4 5 6 7
GPIO0 MSK GPIO1 MSK GPIO2 MSK GPIO3 MSK GPIO4 MSK GPIO5 MSK GPIO6 MSK GPIO7 MSK Wakeup Source C Mask Register
GPIO Edge Selection A Register GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 0 1 2 3 4 5 6 7 Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) 0 1 2 3 4 5 6 7
GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 Wakeup Source D Register
0 1 2 3 4 5 6 7
GPIO8 MSK GPIO9 MSK GPIO10 MSK GPIO11 MSK GPIO12 MSK GPIO13 MSK GPIO14 MSK GPIO15 MSK Wakeup Source D Mask Register
INT3
GPIO Edge Selection B Register GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 0 1 2 3 4 5 6 7 Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) 0 1 2 3 4 5 6 7
GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 Wakeup Source E Register
0 1 2 3 4 5 6 7
GPIO16 MSK GPIO17 MSK GPIO18 MSK GPIO19 MSK GPIO20 MSK GPIO21 MSK GPIO22 MSK GPIO23 MSK Wakeup Source E Mask Register
1245 IntStructure02.0
GPIO Edge Selection C Register
FIGURE
8-2: SST79LF008 Interrupt Structure (int3)
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GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31
0 1 2 3 4 5 6 7
Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F)
0 1 2 3 4 5 6 7
GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 Wakeup Source F Register
0 1 2 3 4 5 6 7
GPIO24 MSK GPIO25 MSK GPIO26 MSK GPIO27 MSK GPIO28 MSK GPIO29 MSK GPIO30 MSK GPIO31 MSK Wakeup Source F Mask Register
GPIO Edge Selection D Register GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 0 1 2 3 4 5 6 7 Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) 0 1 2 3 4 5 6 7
GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 Wakeup Source G Register
0 1 2 3 4 5 6 7
GPIO32 MSK GPIO33 MSK GPIO34 MSK GPIO35 MSK GPIO36 MSK GPIO37 MSK GPIO38 MSK GPIO39 MSK Wakeup Source G Mask Register
GPIO Edge Selection E Register GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 0 1 2 3 4 5 6 7 Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) 0 1 2 3 4 5 6 7
INT4
GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 Wakeup Source H Register
0 1 2 3 4 5 6 7
GPIO40 MSK GPIO41 MSK GPIO42 MSK GPIO43 MSK GPIO44 MSK GPIO45 MSK GPIO46 MSK GPIO47 MSK Wakeup Source H Mask Register
GPIO Edge Selection F Register GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 0 1 2 3 4 5 6 7 Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) 0 1 2 3 4 5 6 7
GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 Wakeup Source I Register
0 1 2 3 4 5 6 7
GPIO48 MSK GPIO49 MSK GPIO50 MSK GPIO51 MSK GPIO52 MSK GPIO53 MSK GPIO54 MSK GPIO55 MSK Wakeup Source I Mask Register
1245 IntStructure03.0
GPIO Edge Selection G Register
FIGURE
8-3: SST79LF008 Interrupt Structure (int4)
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GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63
0 1 2 3 4 5 6 7
Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F)
0 1 2 3 4 5 6 7
GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 Wakeup Source J Register
0 1 2 3 4 5 6 7
GPIO56 MSK GPIO57 MSK GPIO58 MSK GPIO59 MSK GPIO60 MSK GPIO61 MSK GPIO62 MSK GPIO63 MSK Wakeup Source J Mask Register
GPIO Edge Selection H Register GPIO64 GPIO65 GPIO66 GPIO67 GPIO68 GPIO69 GPIO70 GPIO71 0 1 2 3 4 5 6 7 Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) 0 1 2 3 4 5 6 7
GPIO64 GPIO65 GPIO66 GPIO67 GPIO68 GPIO69 GPIO70 GPIO71 Wakeup Source K Register
0 1 2 3 4 5 6 7
GPIO64 MSK GPIO65 MSK GPIO66 MSK GPIO67 MSK GPIO68 MSK GPIO69 MSK GPIO70 MSK GPIO71 MSK Wakeup Source K Mask Register
GPIO Edge Selection I, J Register GPIO72 GPIO73 GPIO74 GPIO75 GPIO76 GPIO77 GPIO78 GPIO79 0 1 2 3 4 5 6 7 Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) 0 1 2 3 4 5 6 7
GPIO72 GPIO73 GPIO74 GPIO75 GPIO76 GPIO77 GPIO78 GPIO79 Wakeup Source L Register
0 1 2 3 4 5 6 7
GPIO72 MSK GPIO73 MSK GPIO74 MSK GPIO75 MSK GPIO76 MSK GPIO77 MSK GPIO78 MSK GPIO79 MSK Wakeup Source L Mask Register
INT5
GPIO Edge Selection K, L Register GPIO80 GPIO81 GPIO82 GPIO83 GPIO84 GPIO85 GPIO86 GPIO87 0 1 2 3 4 5 6 7 Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) 0 1 2 3 4 5 6 7
GPIO80 GPIO81 GPIO82 GPIO83 GPIO84 GPIO85 GPIO86 GPIO87 Wakeup Source M Register
0 1 2 3 4 5 6 7
GPIO80 MSK GPIO81 MSK GPIO82 MSK GPIO83 MSK GPIO84 MSK GPIO85 MSK GPIO86 MSK GPIO87 MSK Wakeup Source M Mask Register
GPIO Edge Selection M, N Register GPIO88 GPIO89 GPIO90 GPIO91 GPIO92 GPIO93 GPIO94 GPIO95 0 1 2 3 4 5 6 7 Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) 0 1 2 3 4 5 6 7
GPIO88 GPIO89 GPIO90 GPIO91 GPIO92 GPIO93 GPIO94 GPIO95 Wakeup Source N Register
0 1 2 3 4 5 6 7
GPIO88 MSK GPIO89 MSK GPIO90 MSK GPIO91 MSK GPIO92 MSK GPIO93 MSK GPIO94 MSK GPIO95 MSK Wakeup Source N Mask Register 1245 IntStructure04.0
GPIO Edge Selection O, P Register
FIGURE
8-4: SST79LF008 Interrupt Structure (int5)
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GPIO96 GPIO97 GPIO98 GPIO99 GPIO100 GPIO101 GPIO102 GPIO103
0 1 2 3 4 5 6 7
Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F) Edge Select (R,F)
0 1 2 3 4 5 6 7
GPIO96 GPIO97 GPIO98 GPIO99 GPIO100 GPIO101 GPIO102 GPIO103 Wakeup Source O Register
0 1 2 3 4 5 6 7
GPIO96 MSK GPIO97 MSK GPIO98 MSK GPIO99 MSK GPIO100 MSK GPIO101 MSK GPIO102 MSK GPIO103 MSK Wakeup Source O Mask Register
GPIO Edge Selection Q, R Register GPIO104 GPIO105 GPIO106 GPIO107 GPIO108 GPIO109 GPIO110 GPIO111 0 1 2 3 4 5 6 7 Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) Edge Select (R,F,RF) 0 1 2 3 4 5 6 7
GPIO104 GPIO105 GPIO106 GPIO107 GPIO108 GPIO109 GPIO110 GPIO111 Wakeup Source P Register
0 1 2 3 4 5 6 7
GPIO104 MSK GPIO105 MSK GPIO106 MSK GPIO107 MSK GPIO108 MSK GPIO109 MSK GPIO110 MSK GPIO111 MSK Wakeup Source P Mask Register
INT5 Extension
GPIO Edge Selection S, T Register
KEYBOARD INT2 INT3 INT4 INT5
0 0 1 2 3
IE0(TCON.1) INT2F INT3F INT4F INT5F EXIF
0 0 1 2 3
EX0(IE.0) EX2 EX3 EX4 EX5 IEA
EA(IE.7) EA EA EA EA
Wake Up from PD Mode
KEYBOARD TIMER0 INT1 TIMER1 UART TIMER2
0 1 2 3 4 5
IE0(TCON.1) TF0(TCON.5) IE1(TCON.3) TF1(TCON.7) TI+RI TF2+EXF2
0 1 2 3 4 5 IE 0 1 2 3 IEA 7
EX0 ET0 EX1 ET1 ES ET2
EA EA EA EA EA EA
TCON, SCON, T2CON INT2 INT3 INT4 INT5 0 1 2 3 EXIF SPI 7 SPIF(SPSR.7) INT2F INT3F INT4F INT5F
To 8051 Interrupt Processing
EX2 EX3 EX4 EX5 EA EA EA EA
SPIE(SPCR.7)
EA 1245 IntStructure05.0
FIGURE
8-5: SST79LF008 Interrupt Structure (int5, pd mode wakeup, 8051 interrupt)
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Advance Information
8.2 SST79LF008 Wakeups
SST79LF008 wake-up sources include LPC cycle start, LPCPD# signal transition, SPI slave clock change, SMBus start condition, PS2 clock falling edge, Matrix keyboard scanner input falling edge, Hibernation timer, FAN tachometers, and programmable GPIOs. All GPIO wake up and interrupt sources are edge sensitive. Active edge for each wake up and interrupt is software specified via the Active Edge Selection registers. Unless explicitly stated otherwise, the GPIO wake up and interrupt requests are not asserted if the alternate function is selected for the respective pin. For detailed information on Interrupt and Wake up Source registers and their associated Mask registers, as well as Active Edge Selection registers, refer to Section 8.3. Refer to Section 9.1 for Alternate Function Select registers. Changes in GPIO configuration, function, or edge selection may generate spurious interrupt requests, which are addressed by software.
8.3 INTERRUPT CONTROL REGISTERS
8.3.1 External Interrupt Flag Register (EXIF)
Location Read ABH Write Reset 7 X 6 X 5 X 4 X 3 INT5F 0 2 INT4F 0 1 INT3F 0 0 INT2F 0
Symbol X INT[5:2]F
Function Not implemented Not defined Interrupt 5-2 flag 1: Interrupt pending 0: No Interrupt
8.3.2 Interrupt Enable Register (IE)
Location Read A8H Write Reset 0 7 EA 6 X 5 ET2 0 4 ES 0 3 ET1 0 2 EX1 0 1 ET0 0 0 EX0 0
Symbol X EA ET2 ES ET1 EX1 ET0 EX0
Function Not implemented Not defined Enable Global Interrupt Enable Timer 2 Interrupt Enable UART Interrupt Enable Timer 1 Interrupt Enable Interrupt 1 Enable Timer 0 Interrupt Enable Interrupt 0 1: Enable Interrupt 0: Disable Interrupt
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Advance Information 8.3.3 Interrupt Enable Register A (IEA)
Location Read E8H Write Reset 7 X 6 X 5 X 4 X 3 EX5 0 2 EX4 0 1 EX3 0 0 EX2 0
Symbol X EX[5:2]
Function Not implemented Not defined Enable Interrupt 5-2 1: Enable Interrupt 0: Disable Interrupt
8.3.4 Interrupt Priority Register (IP)
Location Read B8H Write Reset 0 7 PSPI 6 X 5 PT2 0 4 PS 0 3 PT1 0 2 PX1 0 1 PT0 0 0 PX0 0
Symbol X PSPI PT2 PS PT1 PX1 PT0 PX0 8.3.5 Interrupt Priority High (IPH)
Location Read B7H Write Reset 0 7 PSPIH
Function Not implemented Not defined SPI Interrupt Priority Bit Timer 2 Interrupt Priority Bit UART Interrupt Priority Bit Timer 1 Interrupt Priority Bit Interrupt 1 Priority Bit Timer 0 Interrupt Priority Bit Interrupt 0 Priority Bit
6 X
5 PT2H 0
4 PSH 0
3 PT1H 0
2 PX1H 0
1 PT0H 0
0 PX0H 0
Symbol X PSPIH PT2H PSH PT1H PX1H PT0H PX0H
Function Not implemented Not defined SPI Interrupt Priority Bit High, with PSPI provides 4 Level Priority (11b = highest) Timer 2 Interrupt Priority Bit High, with PT2 provides 4 Level Priority (11b = highest) UART Interrupt Priority Bit High, with PS provides 4 Level Priority (11b = highest) Timer 1 Interrupt Priority Bit High, with PT1 provides 4 Level Priority (11b = highest) Interrupt 1 Priority Bit High, with PX1 provides 4 Level Priority (11b = highest) Timer 0 Interrupt Priority Bit High, with PT0 provides 4 Level Priority (11b = highest) Interrupt 0 Priority Bit High, with PX0 provides 4 Level Priority (11b = highest)
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Advance Information 8.3.6 Interrupt Priority Register A (IPA)
Location Read F8H Write Reset 7 X 6 X 5 X 4 X 3 PX5 0 2 PX4 0 1 PX3 0 0 PX2 0
Symbol X PX[5:2]
Function Not implemented Not defined Interrupt 5-2 Priority bits
8.3.7 Interrupt Priority High Register A (IPAH)
Location Read F7H Write Reset 7 X 6 X 5 X 4 X 3 PX5H 0 2 PX4H 0 1 PX3H 0 0 PX2H 0
Symbol X PX[5:2]H
Function Not implemented Not defined External Interrupt 5-2 Priority Bit High, with PX[5:2] provide 4 Level Priority (11b = highest)
8.3.8 Interrupt Source Register A (INTSRCA)
Location 7F00H Read Write Reset 7 KCOBE 1 6 KCIBF 0 5 SM1INT 0 4 SM0INT 0 3 X 2 ADCINT 0 1 CLKINT 0 0 WDT 0
Symbol X KCOBE KCIBF SM1INT SM0INT ADCINT CLKINT WDT
Function Not implemented Not defined Keyboard controller OBE (Output Buffer Empty) interrupt flag. Set when OBF bit in KBCSTS register is `0', cleared when OBF bit is `1'. Keyboard controller IBF (Input Buffer Full) interrupt flag. Set when IBF bit in KBCSTS register is `1', cleared when IBF bit is `0'. SMBus channel 1 or 2 interrupt flag. Set when INT bit in SMCR1 register is `1', cleared when INT bit is `0'. SMBus channel 0 interrupt flag. Set when INT bit in SMCR0 register is `1', cleared when INT bit is `0'. A/D conversion completion interrupt flag. Set when ADF bit in ADCSR register is `1', cleared when ADF bit is `0'. Clock source change interrupt flag. Set when PLLOK bit changes from `0' to `1', or on any change of ECLOK bit. Write `0' to clear. Writing `1' to this bit will be ignored. Watchdog timer underflow flag. Set when WDT underflows, cleared when WDT is reloaded or disabled.
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Advance Information 8.3.9 Interrupt Source A Mask Register (INTSRCAMSK)
Location Read 7F01H Write Reset 7 KCOBE MSK 0 6 KCIBF MSK 0 5 SM1INT MSK 0 4 SM0INT MSK 0 3 X 2 ADCINT MSK 0 1 CLKINT MSK 0 0 WDT MSK 0
Symbol X KCOBEMSK, ..., WDTMSK
Function Not implemented Not defined Interrupt Source Mask 1: Enable Interrupt from the respective source in INTSRCA register 0: Mask Interrupt source
8.3.10 Interrupt Source Register B (INTSRCB)
Location 7F02H Read Write Reset 7 ECOBE 1 6 ECIBF 0 5 MBXINT 0 4 ECOBE1 1 3 ECIBF1 0 2 PS22INT 0 1 PS21INT 0 0 PS20INT 0
Symbol ECOBE ECIBF MBXINT ECOBE1 ECIBF1 PS22INT
PS21INT
PS20INT
Function Not implemented ACPI ECI channel 0 Output Buffer Empty interrupt flag. Set when OBF bit in ECISTS register is `0', cleared when OBF bit is `1'. ACPI ECI channel 0 Input Buffer Full interrupt flag. Set when IBF bit in ECISTS register is `1', cleared when IBF bit is `0'. Mailbox interface System-to-8051interrupt. Set when the system writes to Mailbox register 0, cleared when 8051 reads Mailbox register 0. ACPI ECI channel 1 Output Buffer Empty interrupt flag. Set when OBF bit in ECISTS1 register is `0', cleared when OBF bit is `1'. ACPI ECI channel 1 Input Buffer Full interrupt flag. Set when IBF bit in ECISTS1 register is `1', cleared when IBF bit is `0'. PS2 channel 2 interrupt If PS/2 h/w state machine is enabled, set by `0' to `1' transition of any of the following bits in PS2STS2 register: PS2STSn_RDATA_RDY, PS2STSn_XMIT_IDLE, PS2STSn_R_TIMEOUT or PS2STSn_T_TIMEOUT. If PS/2 h/w state machine is disabled, set by falling edge on PSCLK2 pin driven by the peripheral. Cleared by reading PS2STS2 register (in any mode of PS2 h/w state machine). PS2 channel 1 interrupt If PS/2 h/w state machine is enabled, set by `0' to `1' transition of any of the following bits in PS2STS1 register: PS2STSn_RDATA_RDY, PS2STSn_XMIT_IDLE, PS2STSn_R_TIMEOUT or PS2STSn_T_TIMEOUT. If PS/2 h/w state machine is disabled, set by falling edge on PSCLK1 pin driven by the peripheral. Cleared by reading PS2STS1 register (in any mode of PS2 h/w state machine). PS2 channel 0 interrupt If PS/2 h/w state machine is enabled, set by `0' to `1' transition of any of the following bits in PS2STS0 register: PS2STSn_RDATA_RDY, PS2STSn_XMIT_IDLE, PS2STSn_R_TIMEOUT or PS2STSn_T_TIMEOUT. If PS/2 h/w state machine is disabled Set by falling edge on PSCLK0 pin driven by the peripheral. Cleared by reading PS2STS0 register (in any mode of PS2 h/w state machine).
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Advance Information 8.3.11 Interrupt Source B Mask Register (INTSRCBMSK)
Location Read 7F03H Write Reset 7 ECOBE MSK 0 6 ECIBF MSK 0 5 MBXINT MSK 0 4 ECOBE1 MSK 0 3 ECIBF1 MSK 0 2 PS22INT MSK 0 1 PS21INT MSK 0 0 PS20INT MSK 0
Symbol ECOBEMSK, ..., PS20INTMSK
Function Interrupt Source Mask 1: Enable Interrupt from the respective source in INTSRCB register 0: Mask Interrupt source
8.3.12 Wakeup Source A Register (WSRCA)
Location Read 7F2AH Write Reset 7 SMB0_ DATA 0 6 5 4 3 SPICLK 0 2 X 1 HIB_TO 1 0 LPC 0 PS2_ SB2 PS2_ SB1 PS2_ SB0 0 0 0
Symbol X SMB0_DATA
PS2_SB2
PS2_SB1
PS2_SB0
SPICLK
HIB_TO LPC
Function Not implemented Not defined SMBus channel 0 start condition detection flag. Set when start condition is detected Write `0' to clear. Writing `1' to this bit will be ignored. PS2 channel 2 start bit detection flag. Set by falling edge on PSCLK2 pin driven by the peripheral (in any mode of PS2 h/w state machine). Write `0' to clear. Writing `1' to this bit will be ignored. PS1 channel 1 start bit detection flag. Set by falling edge on PSCLK1 pin driven by the peripheral (in any mode of PS2 h/w state machine). Write `0' to clear. Writing `1' to this bit will be ignored. PS2 channel 0 start bit detection flag. Set by falling edge on PSCLK0 pin driven by the peripheral (in any mode of PS2 h/w state machine). Write `0' to clear. Writing `1' to this bit will be ignored. SPI clock edge detection flag (in SPI slave mode). Set when any transition of SPI Clock (SCK) or SPI port Select (SS#) signal is detected. Write `0' to clear. Writing `1' to this bit will be ignored. Hibernation timer time out flag. Set when Hibernation timer underflows, cleared when Hibernation timer is restarted. LPC LFRAME# falling edge detection flag. Set when falling edge is detected. Write `0' to clear. Writing `1' to this bit will be ignored.
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Advance Information 8.3.13 Wakeup Source A Wakeup Mask Register (WSRCAMSK)
Location Read 7F2BH Write Reset 7 SMB0_ DATA_MS K 0 6 PS2_SB2 _MSK 0 5 PS2_SB1 _MSK 0 4 PS2_SB0 _MSK 0 3 SPICLK_ MSK 0 2 X 0 0 1 HIB_MSK 0 LPC_MSK
Symbol X SMB0_DATA_MSK,
PS2_SB2_MSK
PS2_SB1_MSK
PS2_SB0_MSK
SPICLK_MSK
HIB_MSK
LPC_MSK
Function Not implemented Not defined Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt from the respective source in WSRCA register 0: Mask Wakeup and Interrupt source Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt from the respective source in WSRCA register 0: Mask Wakeup and Interrupt source Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt from the respective source in WSRCA register 0: Mask Wakeup and Interrupt source Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt from the respective source in WSRCA register 0: Mask Wakeup and Interrupt source Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt from the respective source in WSRCA register 0: Mask Wakeup and Interrupt source Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt from the respective source in WSRCA register 0: Mask Wakeup and Interrupt source Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt from the respective source in WSRCA register 0: Mask Wakeup and Interrupt source
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Advance Information 8.3.14 Wakeup Source B Register (WSRCB)
Location Read 7F2CH Write Reset 7 FAN2 0 6 FAN1 0 5 X 4 X 3 LRESET 0 2 aLPCINT 0 1 SMB2_ DATA 0 0 SMB1_ DATA 0
Symbol X FAN[2:1]
LRESET aLPCINT
SMB2_DATA
SMB1_DATA
Function Not implemented Not defined FAN Tachometer [2:1] threshold detection flag. Set when FAN tachometer counter exceeds the threshold, cleared when counter is reloaded with value below threshold. LPC LRESET# falling edge detection flag. Set when falling edge is detected. Write `0' to clear. Writing `1' to this bit will be ignored. aLPC Enable_and_Poll sequence detection flag. Set when Enable_and_Poll sequence is received over aLPC bus. Write `0' to clear. Writing `1' to this bit will be ignored. SMBus channel 2 start condition detection flag. Set when start condition is detected. Write `0' to clear. Writing `1' to this bit will be ignored. SMBus channel 1 start condition detection flag. Set when start condition is detected. Write `0' to clear. Writing `1' to this bit will be ignored.
8.3.15 Wakeup Source B Mask Register (WSRCBMSK)
Location Read 7F2DH Write Reset 0 0 7 6 5 X 4 X 3 LRESET_ MSK 0 2 aLPCIN MSK X 1 SMB2_ MSK 0 0 SMB1_ MSK 0 FAN2MSK FAN1MSK
Symbol X FAN2MSK, ..., SMB1_MSK
Function Not implemented Not defined Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt from the respective source in WSRCB register 0: Mask Wakeup and Interrupt source
8.3.16 Keyboard Wakeup Control Register (KEYWSRC)
Location Read 7F2FH Write Reset 7 X 6 X 5 X 4 X 3 X 2 X 1 KEYMSK 0 0 KEY 0
Symbol X KEYMSK
KEY
Function Not implemented Not defined Keystroke Wake up and Interrupt Source Mask 1: Enable Wake up and Interrupt when KEY bit is set 0: Mask and keystroke Wake up and Interrupt Keystroke press detection flag. Set when falling edge on any scanner input lines KSI[7:0] is detected. Write `0' to clear. Writing `1' to this bit will be ignored.
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Advance Information 8.3.17 Wakeup Source C Register (WSRCC)
Location Read 7F59H Write Reset 0 0 0 0 0 0 0 0 7 GPIO7 6 GPIO6 5 GPIO5 4 GPIO4 3 GPIO3 2 GP102 1 GPIO1 0 GPIO0
Symbol GPIO[7:0]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
8.3.18 Wakeup Source C Mask Register (WSRCCMSK)
Location Read 7F5AH Write Reset 7 GPIO7_ MSK 0 6 GPIO6_ MSK 0 5 GPIO5_ MSK 0 4 GPIO4_ MSK 0 3 GPIO3_ MSK 0 2 GPIO2_ MSK 0 1 GPIO1_ MSK 0 0 GPIO0_ MSK 0
Symbol GPIO[7:0]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
8.3.19 GPIO Active Edge Selection Register A (GPIOESA)
Location Read 7F57H Write Reset 7 GPIO7_ ES 0 6 GPIO6_ ES 0 5 GPIO5_ ES 0 4 GPIO4_ ES 0 3 GPIO3_ ES 0 2 GPIO2_ ES 0 1 GPIO1_ ES 0 0 GPIO0_ ES 0
Symbol GPIO[7:0]_ES
Function GPIO active edge control bit 1: Select Rising edge (Low to High transition) 0: Select Falling edge (High to Low transition)
8.3.20 Wakeup Source D Register (WSRCD)
Location Read 7F5EH Write Reset 0 0 0 0 0 0 0 0 7 GPIO15 6 GPIO14 5 GPIO13 4 GPIO12 3 GPIO11 2 GPIO10 1 GPIO9 0 GPIO8
Symbol GPIO[15:8]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
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Advance Information 8.3.21 Wakeup Source D Mask Register (WSRCDMSK)
Location Read 7F5FH Write Reset 7 GPIO15_ MSK 0 6 GPIO14_ MSK 0 5 GPIO13_ MSK 0 4 GPIO12_ MSK 0 3 GPIO11_ MSK 0 2 GPIO10_ MSK 0 1 GPIO9_ MSK 0 0 GPIO8_ MSK 0
Symbol GPIO[15:8]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
8.3.22 GPIO Active Edge Selection Register B (GPIOESB)
Location Read 7F58H Write Reset 7 GPIO15_ ES 0 6 GPIO14_ ES 0 5 GPIO13_ ES 0 4 GPIO12_ ES 0 3 GPIO11_ ES 0 2 GPIO10_ ES 0 1 GPIO9_ ES 0 0 GPIO8_ ES 0
Symbol GPIO[15:8]_ES
Function GPIO active edge control bit 1: Select Rising edge (Low to High transition) 0: Select Falling edge (High to Low transition)
8.3.23 Wakeup Source E Register (WSRCE)
Location Read 7F63H Write Reset 0 0 0 0 0 0 0 0 7 GPIO23 6 GPIO22 5 GPIO21 4 GPIO20 3 GPIO19 2 GPIO18 1 GPIO17 0 GPIO16
Symbol GPIO[23:16]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
8.3.24 Wakeup Source E Mask Register (WSRCEMSK)
Location Read 7F66H Write Reset 7 GPIO23_ MSK 0 6 GPIO22_ MSK 0 5 GPIO21_ MSK 0 4 GPIO20_ MSK 0 3 GPIO19_ MSK 0 2 GPIO18_ MSK 0 1 GPIO17_ MSK 0 0 GPIO16_ MSK 0
Symbol GPIO[23:16]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
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Advance Information 8.3.25 GPIO Active Edge Selection Register C (GPIOESC)
Location Read 7F5CH Write Reset 7 GPIO23_ ES 0 6 GPIO22_ ES 0 5 GPIO21_ ES 0 4 GPIO20_ ES 0 3 GPIO19_ ES 0 2 GPIO18_ ES 0 1 GPIO17_ ES 0 0 GPIO16_ ES 0
Symbol GPIO[23:16]_ES
Function GPIO active edge control bit 1: Select Rising edge (Low to High transition) 0: Select Falling edge (High to Low transition)
8.3.26 Wakeup Source F Register (WSRCF)
Location Read 7F64H Write Reset 0 0 0 0 0 0 0 0 7 GPIO31 6 GPIO30 5 GPIO29 4 GPIO28 3 GPIO27 2 GPIO26 1 GPIO25 0 GPIO24
Symbol GPIO[31:24]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
8.3.27 Wakeup Source F Mask Register (WSRCFMSK)
Location Read 7F65H Write Reset 7 GPIO31_ MSK 0 6 GPIO30_ MSK 0 5 GPIO29_ MSK 0 4 GPIO28_ MSK 0 3 GPIO27_ MSK 0 2 GPIO26_ MSK 0 1 GPIO25_ MSK 0 0 GPIO24_ MSK 0
Symbol GPIO[31:24]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
8.3.28 GPIO Active Edge Selection Register D (GPIOESD)
Location Read 7F5DH Write Reset 7 GPIO31_ ES 0 6 GPIO30_ ES 0 5 GPIO29_ ES 0 4 GPIO28_ ES 0 3 GPIO27_ ES 0 2 GPIO26_ ES 0 1 GPIO25_ ES 0 0 GPIO24_ ES 0
Symbol GPIO[31:24]_ES
Function GPIO active edge control bit 1: Select Rising edge (Low to High transition) 0: Select Falling edge (High to Low transition)
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Advance Information 8.3.29 Wakeup Source G Register (WSRCG)
Location Read 7F55H
1.
7 GPIO39 0 Write Reset
6 GPIO38/ LPCPD1 0
5 GPIO37 0
4 GPIO36 0
3 GPIO35 0
2 GPIO34 0
1 GPIO33 0
0 GPIO32 0
This interrupt source bit is set when active edge is detected regardless of whether GPIO38 or alternate LPCPD# function is selected
Symbol GPIO[39:32]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
8.3.30 Wakeup Source G Mask Register (WSRCGMSK)
Location Read 7F56H Write Reset 7 GPIO39_ MSK 0 6 GPIO38_ MSK 0 5 GPIO37_ MSK 0 4 GPIO36_ MSK 0 3 GPIO35_ MSK 0 2 GPIO34_ MSK 0 1 GPIO33_ MSK 0 0 GPIO32_ MSK 0
Symbol GPIO[39:32]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
8.3.31 GPIO Active Edge Selection Register E (GPIOESE)
Location Read 7F60H Write Reset 7 GPIO39_ ES 0 6 GPIO38_ ES 0 5 GPIO37_ ES 0 4 GPIO36_ ES 0 3 GPIO35_ ES 0 2 GPIO34_ ES 0 1 GPIO33_ ES 0 0 GPIO32_ ES 0
Symbol GPIO[39:32]_ES
Function GPIO active edge control bit 1: Select Rising edge (Low to High transition) 0: Select Falling edge (High to Low transition)
8.3.32 Wakeup Source H Register (WSRCH)
Location Read 7FAEH Write Reset 0 0 0 0 0 0 0 0 7 GPIO47 6 GPIO46 5 GPIO45 4 GPIO44 3 GPIO43 2 GPIO42 1 GPIO41 0 GPIO40
Symbol GPIO[47:40]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
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Advance Information 8.3.33 Wakeup Source H Mask Register (WSRCHMSK)
Location Read 7FAFH Write Reset 7 GPIO47_ MSK 0 6 GPIO46_ MSK 0 5 GPIO45_ MSK 0 4 GPIO44_ MSK 0 3 GPIO43_ MSK 0 2 GPIO42_ MSK 0 1 GPIO41_ MSK 0 0 GPIO40_ MSK 0
Symbol GPIO[47:40]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
8.3.34 GPIO Active Edge Selection Register F (GPIOESF)
Location Read 7F61H Write Reset 7 GPIO47_ ES 0 6 GPIO46_ ES 0 5 GPIO45_ ES 0 4 GPIO44_ ES 0 3 GPIO43_ ES 0 2 GPIO42_ ES 0 1 GPIO41_ ES 0 0 GPIO40_ ES 0
Symbol GPIO[47:40]_ES
Function GPIO active edge control bit 1: Select Rising edge (Low to High transition) 0: Select Falling edge (High to Low transition)
8.3.35 Wakeup Source I Register (WSRCI)
Location Read 7F3EH Write Reset 0 0 0 0 0 0 0 0 7 GPIO55 6 GPIO54 5 GPIO53 4 GPIO52 3 GPIO51 2 GPIO50 1 GPIO49 0 GPIO48
Symbol GPIO[55:48]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
8.3.36 Wakeup Source I Mask Register (WSRCIMSK)
Location Read 7F3FH Write Reset 7 GPIO55_ MSK 0 6 GPIO54_ MSK 0 5 GPIO53_ MSK 0 4 GPIO52_ MSK 0 3 GPIO51_ MSK 0 2 GPIO50_ MSK 0 1 GPIO49_ MSK 0 0 GPIO48_ MSK 0
Symbol GPIO[55:48]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
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Advance Information 8.3.37 GPIO Active Edge Selection Register G (GPIOESG)
Location Read 7F62H Write Reset 7 GPIO55_ ES 0 6 GPIO54_ ES 0 5 GPIO53_ ES 0 4 GPIO52_ ES 0 3 GPIO51_ ES 0 2 GPIO50_ ES 0 1 GPIO49_ ES 0 0 GPIO48_ ES 0
Symbol GPIO[55:48]_ES
Function GPIO active edge control bit 1: Select Rising edge (Low to High transition) 0: Select Falling edge (High to Low transition)
8.3.38 Wakeup Source J Register (WSRCJ)
Location Read 7FC8H Write Reset 0 0 0 0 0 0 0 0 7 GPIO63 6 GPIO62 5 GPIO61 4 GPIO60 3 GPIO59 2 GPIO58 1 GPIO57 0 GPIO56
Symbol GPIO[63:56]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
8.3.39 Wakeup Source J Mask Register (WSRCJMSK)
Location Read 7FC9H Write Reset 7 GPIO63_ MSK 0 6 GPIO62_ MSK 0 5 GPIO61_ MSK 0 4 GPIO60_ MSK 0 3 GPIO59_ MSK 0 2 GPIO58_ MSK 0 1 GPIO57_ MSK 0 0 GPIO56_ MSK 0
Symbol GPIO[63:56]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
8.3.40 GPIO Active Edge Selection Register H (GPIOESH)
Location Read 7F6CH Write Reset 7 GPIO63_ ES 0 6 GPIO62_ ES 0 5 GPIO61_ ES 0 4 GPIO60_ ES 0 3 GPIO59_ ES 0 2 GPIO58_ ES 0 1 GPIO57_ ES 0 0 GPIO56_ ES 0
Symbol GPIO[63:56]_ES
Function GPIO active edge control bit 1: Select Rising edge (Low to High transition) 0: Select Falling edge (High to Low transition)
8.3.41 Wakeup Source K Register (WSRCK)
Location Read 7FCAH Write Reset 0 0 0 0 0 0 0 0 7 GPIO71 6 GPIO70 5 GPIO69 4 GPIO68 3 GPIO67 2 GPIO66 1 GPIO65 0 GPIO64
Symbol GPIO[71:64]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
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Advance Information 8.3.42 Wakeup Source K Mask Register (WSRCKMSK)
Location Read 7FCBH Write Reset 7 GPIO71_ MSK 0 6 GPIO70_ MSK 0 5 GPIO69_ MSK 0 4 GPIO68_ MSK 0 3 GPIO67_ MSK 0 2 GPIO66_ MSK 0 1 GPIO65_ MSK 0 0 GPIO64_ MSK 0
Symbol GPIO[71:64]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
8.3.43 GPIO Active Edge Selection Register I (GPIOESI)
Location Read 7F6DH Write Reset 7 GPIO67_ ES1 0 6 GPIO67_ ES0 0 5 GPIO66_ ES1 0 4 GPIO66_ ES0 0 3 GPIO65_ ES1 0 2 GPIO65_ ES0 0 1 GPIO64_ ES1 0 0 GPIO64_ ES0 0
Symbol GPIO[67:64]_ES[1:0]
Function GPIO active edge control bit 01: Select Rising edge (Low to High transition) 10: Select Both Falling and Rising Edges 00 or 11: Select Falling edge (High to Low transition)
8.3.44 GPIO Active Edge Selection Register J (GPIOESJ)
Location Read 7F6EH Write Reset 7 GPIO71_ ES1 0 6 GPIO71_ ES0 0 5 GPIO70_ ES1 0 4 GPIO70_ ES0 0 3 GPIO69_ ES1 0 2 GPIO69_ ES0 0 1 GPIO68_ ES1 0 0 GPIO68_ ES0 0
Symbol GPIO[71:68]_ES[1:0]
Function GPIO active edge control bit 01: Select Rising edge (Low to High transition) 10: Select Both Falling and Rising Edges 00 or 11: Select Falling edge (High to Low transition)
8.3.45 Wakeup Source L Register (WSRCL)
Location Read 7FCCH Write Reset 0 0 0 0 0 0 0 0 7 GPIO79 6 GPIO78 5 GPIO77 4 GPIO76 3 GPIO75 2 GPIO74 1 GPIO73 0 GPIO72
Symbol GPIO[79:72]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
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Advance Information 8.3.46 Wakeup Source L Mask Register (WSRCLMSK)
Location Read 7FCDH Write Reset 7 GPIO79_ MSK 0 6 GPIO78_ MSK 0 5 GPIO77_ MSK 0 4 GPIO76_ MSK 0 3 GPIO75_ MSK 0 2 GPIO74_ MSK 0 1 GPIO73_ MSK 0 0 GPIO72_ MSK 0
Symbol GPIO[79:72]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
8.3.47 GPIO Active Edge Selection Register K (GPIOESK)
Location Read 7F6FH Write Reset 7 GPIO75_ ES1 0 6 GPIO75_ ES0 0 5 GPIO74_ ES1 0 4 GPIO74_ ES0 0 3 GPIO73_ ES1 0 2 GPIO73_ ES0 0 1 GPIO72_ ES1 0 0 GPIO72_ ES0 0
Symbol GPIO[75:72]_ES[1:0]
Function GPIO active edge control bit 01: Select Rising edge (Low to High transition) 10: Select Both Falling and Rising Edges 00 or 11: Select Falling edge (High to Low transition)
8.3.48 GPIO Active Edge Selection Register L (GPIOESL)
Location Read 7FD0H Write Reset 7 GPIO79_ ES1 0 6 GPIO79_ ES0 0 5 GPIO78_ ES1 0 4 GPIO78_ ES0 0 3 GPIO77_ ES1 0 2 GPIO77_ ES0 0 1 GPIO76_ ES1 0 0 GPIO76_ ES0 0
Symbol GPIO[79:76]_ES[1:0]
Function GPIO active edge control bit 01: Select Rising edge (Low to High transition) 10: Select Both Falling and Rising Edges 00 or 11: Select Falling edge (High to Low transition)
8.3.49 Wakeup Source M Register (WSRCM)
Location Read 7FCEH Write Reset 0 0 0 0 0 0 0 0 7 GPIO87 6 GPIO86 5 GPIO85 4 GPIO84 3 GPIO83 2 GPIO82 1 GPIO81 0 GPIO80
Symbol GPIO[87:80]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
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Advance Information 8.3.50 Wakeup Source M Mask Register (WSRCMMSK)
Location Read 7FCFH Write Reset 7 GPIO87_ MSK 0 6 GPIO86_ MSK 0 5 GPIO85_ MSK 0 4 GPIO84_ MSK 0 3 GPIO83_ MSK 0 2 GPIO82_ MSK 0 1 GPIO81_ MSK 0 0 GPIO80_ MSK 0
Symbol GPIO[87:80]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
8.3.51 GPIO Active Edge Selection Register M (GPIOESM)
Location Read 7FD1H Write Reset 7 GPIO83_ ES1 0 6 GPIO83_ ES0 0 5 GPIO82_ ES1 0 4 GPIO82_ ES0 0 3 GPIO81_ ES1 0 2 GPIO81_ ES0 0 1 GPIO80_ ES1 0 0 GPIO80_ ES0 0
Symbol GPIO[83:80]_ES[1:0]
Function GPIO active edge control bit 01: Select Rising edge (Low to High transition) 10: Select Both Falling and Rising Edges 00 or 11: Select Falling edge (High to Low transition)
8.3.52 GPIO Active Edge Selection Register N (GPIOESN)
Location Read 7FD2H Write Reset 7 GPIO87_ ES1 0 6 GPIO87_ ES0 0 5 GPIO86_ ES1 0 4 GPIO86_ ES0 0 3 GPIO85_ ES1 0 2 GPIO85_ ES0 0 1 GPIO84_ ES1 0 0 GPIO84_ ES0 0
Symbol GPIO[87:84]_ES[1:0]
Function GPIO active edge control bit 01: Select Rising edge (Low to High transition) 10: Select Both Falling and Rising Edges 00 or 11: Select Falling edge (High to Low transition)
8.3.53 GPIO K Interrupt Selection Register (GPIOKINT)
Location Read 7FB8H Write Reset 7 X 6 X 5 GPIO85IN T 0 4 GPIO84IN T 0 3 GPIO83IN T 0 2 GPIO82IN T 0 1 GPIO81IN T 0 0 GPIO80IN T 0
Symbol X GPIO[85:80]INT
Function Not implemented Not defined GPIO Interrupt control bit 1: GPIO active edge detection generates INT0 (combined with any KEY press detection interrupt) 0: GPIO active edge detection generates INT5 (as shown on Figure 8-1)
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Advance Information 8.3.54 Wakeup Source N Register (WSRCN)
Location Read 7FB0H Write Reset X 0 0 0 0 0 0 0 7 GPIO95 6 GPIO94 5 GPIO93 4 GPIO92 3 GPIO91 2 GPIO90 1 GPIO89 0 GPIO88
Symbol X GPIO[95:88]
Function Not defined GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
8.3.55 Wakeup Source N Mask Register (WSRCNMSK)
Location Read 7FB1H Write Reset 7 GPIO95_ MSK X 6 GPIO94_ MSK 0 5 GPIO93_ MSK 0 4 GPIO92_ MSK 0 3 GPIO91_ MSK 0 2 GPIO90_ MSK 0 1 GPIO89_ MSK 0 0 GPIO88_ MSK 0
Symbol X GPIO[95:88]_MSK
Function Not defined GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
8.3.56 GPIO Active Edge Selection Register O (GPIOESO)
Location Read 7FD3H Write Reset 7 GPIO91_ ES1 0 6 GPIO91_ ES0 0 5 GPIO90_ ES1 0 4 GPIO90_ ES0 0 3 GPIO89_ ES1 0 2 GPIO89_ ES0 0 1 GPIO88_ ES1 0 0 GPIO88_ ES0 0
Symbol GPIO[91:88]_ES[1:0]
Function GPIO active edge control bit 01: Select Rising edge (Low to High transition) 10: Select Both Falling and Rising Edges 00 or 11: Select Falling edge (High to Low transition)
8.3.57 GPIO Active Edge Selection Register P (GPIOESP)
Location Read 7FD4H Write Reset 7 GPIO95_ ES1 0 6 GPIO95_ ES0 0 5 GPIO94_ ES1 0 4 GPIO94_ ES0 0 3 GPIO93_ ES1 0 2 GPIO93_ ES0 0 1 GPIO92_ ES1 0 0 GPIO92_ ES0 0
Symbol GPIO[95:92]_ES[1:0]
Function GPIO active edge control bit 01: Select Rising edge (Low to High transition) 10: Select Both Falling and Rising Edges 00 or 11: Select Falling edge (High to Low transition)
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Advance Information 8.3.58 Wakeup Source O Register (WSRCO)
Location Read 7FDBH Write Reset 0 0 0 0 0 0 0 0 7 GPIO103 6 GPIO102 5 GPIO101 4 GPIO100 3 GPIO99 2 GPIO98 1 GPIO97 0 GPIO96
Symbol GPIO[103:96]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
8.3.59 Wakeup Source O Mask Register (WSRCOMSK)
Location Read 7FECH Write Reset 7 GPIO103 _MSK 0 6 GPIO102 _MSK 0 5 GPIO101 _MSK 0 4 GPIO100 _MSK 0 3 GPIO99_ MSK 0 2 GPIO98_ MSK 0 1 GPIO97_ MSK 0 0 GPIO96_ MSK 0
Symbol GPIO[103:96]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
8.3.60 GPIO Active Edge Selection Register Q (GPIOESQ)
Location Read 7FD5H Write Reset 7 GPIO99_ ES1 0 6 GPIO99_ ES0 0 5 GPIO98_ ES1 0 4 GPIO98_ ES0 0 3 GPIO97_ ES1 0 2 GPIO97_ ES0 0 1 GPIO96_ ES1 0 0 GPIO96_ ES0 0
Symbol GPIO[99:96]_ES[1:0]
Function GPIO active edge control bit 01: Select Rising edge (Low to High transition) 10: Select Both Falling and Rising Edges 00 or 11: Select Falling edge (High to Low transition)
8.3.61 GPIO Active Edge Selection Register R (GPIOESR)
Location Read 7FD6H Write Reset 7 GPIO103 _ES1 0 6 GPIO103 _ES0 0 5 GPIO102 _ES1 0 4 GPIO102 _ES0 0 3 GPIO101 _ES1 0 2 GPIO101 _ES0 0 1 GPIO100 _ES1 0 0 GPIO100 _ES0 0
Symbol GPIO[103:100] _ES[1:0]
Function GPIO active edge control bit 01: Select Rising edge (Low to High transition) 10: Select Both Falling and Rising Edges 00 or 11: Select Falling edge (High to Low transition)
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Advance Information 8.3.62 Wakeup Source P Register (WSRCP)
Location Read 7FEDH Write Reset 0 0 0 0 0 0 0 0 7 GPIO111 6 GPIO110 5 GPIO109 4 GPIO108 3 GPIO107 2 GPIO106 1 GPIO105 0 GPIO104
Symbol GPIO[111:104]
Function GPIO active edge detection flag. Set when selected edge is detected. Write 0 to clear. Writing 1 to this bit will be ignored.
8.3.63 Wakeup Source P Mask Register (WSRCPMSK)
Location Read 7FEEH Write Reset 7 GPIO111 _MSK 0 6 GPIO110 _MSK 0 5 GPIO109 _MSK 0 4 GPIO108 _MSK 0 3 GPIO107 _MSK 0 2 GPIO106 _MSK 0 1 GPIO105 _MSK 0 0 GPIO104 _MSK 0
Symbol GPIO[111:104]_MSK
Function GPIO Wakeup and Interrupt Source Mask 1: Enable Wakeup and Interrupt when GPIO edge detection flag is set 0: Mask GPIO Wakeup and Interrupt
8.3.64 GPIO Active Edge Selection Register S (GPIOESS)
Location Read 7FD7H Write Reset 7 GPIO107 _ES1 0 6 GPIO107 _ES0 0 5 GPIO106 _ES1 0 4 GPIO106 _ES0 0 3 GPIO105 _ES1 0 2 GPIO105 _ES0 0 1 GPIO104 _ES1 0 0 GPIO104 _ES0 0
Symbol GPIO[107:104] _ES[1:0]
Function GPIO active edge control bit 01: Select Rising edge (Low to High transition) 10: Select Both Falling and Rising Edges 00 or 11: Select Falling edge (High to Low transition)
8.3.65 GPIO Active Edge Selection Register T (GPIOEST)
Location Read 7FD8H Write Reset 7 GPIO111 _ES1 0 6 GPIO111 _ES0 0 5 GPIO110 _ES1 0 4 GPIO110 _ES0 0 3 GPIO109 _ES1 0 2 GPIO109 _ES0 0 1 GPIO108 _ES1 0 0 GPIO108 _ES0 0
Symbol GPIO[111:108] _ES[1:0]
Function GPIO active edge control bit 01: Select Rising edge (Low to High transition) 10: Select Both Falling and Rising Edges 00 or 11: Select Falling edge (High to Low transition)
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Advance Information
9.0 GPIO PORTS
The SST79LF008 has 112 general purpose input/output pins (GPIOs); 77 pins are multiplexed with alternate functions, as shown in to Figure 2-1, and 35 pins are dedicated GPIOs. All GPIO pins also generate 8051 Interrupt and Wake up events. See Section 8.0 for additional information on Interrupt and Wake up control. Use the GPIO Function Selection Registers to select either the GPIO function or an alternate function for the corresponding pins. When an alternate function is selected the direction of the pin as well as output data is determined by the peripheral module that controls the alternate function. When selecting the GPIO function, the direction of the pin is determined by the respective GPIO Direction Register, and the output data for output pins is specified by the respective Output Register. In other words, the status of the pin is controlled by the data in the GPIO Output Register when the GPIO function is selected and output direction is specified). No direction control is provided for GPI43-GPI45 pins, which are always configured as inputs. Also, no direction control is provided for the GPIO16-GPIO22, GPIO28GPIO39, and GPIO40 pins with open drain buffers, which are always configured as outputs. Note: When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part. GPIO60-GPIO79, GPIO88-GPIO91, and GPIO96GPIO111 with push-pull buffers can be used to emulate open drain configuration by tri-stating the push-pull buffer when output data is `1'. The respective open-drain/pushpull selection registers control buffer configuration for these pins. GPIO80-GPIO85 and GPIO94-GPIO111 have programmable pull-up resistors, which can be enabled/disabled by the respective pull-up control registers. For most pins, reading the GPIO input registers will return the status of the pins, regardless of selected function. The only exceptions being, GPIO68-GPIO71 and GPIO72GPIO79 are multiplexed with DAC outputs or ADC inputs are the only exceptions. These pins can be read via input registers in the GPIO mode only. Reading the input register when DAC or ADC alternate function is enabled will return an indeterminate value. For detailed information on GPIO control registers refer to Section 9.1. See also, the GPIO buffer types list in Table 21 and Table 2-2.
9.1 GPIO CONTROL REGISTERS
9.1.1 GPIO A Direction Register (GPIOADIR)
Location Read 7F18H Write Reset 7 GPIO7_ DiR 0 6 GPIO6_ DIR 0 5 GPIO5_ DIR 0 4 GPIO4_ DIR 0 3 GPIO3_ DIR 0 2 GPIO2_ DIR 0 1 GPIO1_ DIR 0 0 GPIO0_ DIR 0
Symbol GPIO[7:0]_DIR
Function GPIO direction control bit 1: Output 0: Input
9.1.2 GPIO A Input Register (GPIOAIN)1
Location 7F1AH Read Write Reset 7 6 5 4 3 2 1 0 GPIO7_IN GPIO6_IN GPIO5_IN GPIO4_IN GPIO3_IN GPIO2_IN GPIO1_IN GPIO0_IN GPIO7_IN GPIO6_IN GPIO5_IN GPIO4_IN GPIO3_IN GPIO2_IN GPIO1_IN GPIO0_IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[7:0]_IN
Function Not implemented When read, returns the status of the pin.
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Advance Information 9.1.3 GPIO A Output Register (GPIOAOUT)
Location Read 7F19H Write Reset 7 GPIO7_ OUT 1 6 GPIO6_ OUT 1 5 GPIO5_ OUT 1 4 GPIO4_ OUT 1 3 GPIO3_ OUT 1 2 GPIO2_ OUT 1 1 GPIO1_ OUT 1 0 GPIO0_ OUT 1
Symbol GPIO[7:0]_OUT
Function When written to, output data is updated. When read, returns previously written data.
9.1.4 GPIO A Function Select Register (GPIOASEL)
Location Read 7F3DH Write Reset 7 GPIO7_ SEL 0 6 GPIO6_ SEL 0 5 GPIO5_ SEL 0 4 GPIO4_ SEL 0 3 GPIO3_ SEL 0 2 GPIO2_ SEL 0 1 GPIO1_ SEL 0 0 GPIO0_ SEL 0
Symbol GPIO7_SEL GPIO6_SEL GPIO5_SEL GPIO4_SEL GPIO3_SEL GPIO2_SEL GPIO1_SEL GPIO0_SEL
Function 1: GA20 (Gate A20 output) 0: GPIO7 function 1: SS# (Slave port select input for SPI) 0: GPIO6 function 1: SCK (Master clock output, slave clock input pin for SPI) 0: GPIO5 function 1: MISO (Master data input pin, slave data output pin for SPI) 0: GPIO4 function 1: MOSI (Master data output pin, slave data input pin for SPI) 0: GPIO3 function 1: PWM2 (Pulse Width Modulator output 2) 0: GPIO2 function 1: PWM1 (Pulse Width Modulator output 1) 0: GPIO1 function 1: PWM0 (Pulse Width Modulator output 0) 0: GPIO0 function
9.1.5 GPIO B Direction Register (GPIOBDIR)
Location Read 7F1BH Write Reset 7 GPIO15_ DIR 0 6 GPIO14_ DIR 0 5 GPIO13_ DIR 0 4 GPIO12_ DIR 0 3 GPIO11_ DIR 0 2 GPIO10_ DIR 0 1 GPIO9_ DIR 0 0 GPIO8_ DIR 0
Symbol GPIO[15:8]_DIR
Function GPIO direction control bit 1: Output 0: Input
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Advance Information 9.1.6 GPIO B Input Register (GPIOBIN)1
Location Read 7F1DH Write Reset 7 GPIO15_ IN GPIO15_ IN 6 GPIO14_ IN GPIO14_ IN 5 GPIO13_ IN GPIO13_ IN 4 GPIO12_ IN GPIO12_ IN 3 GPIO11_ IN GPIO11_ IN 2 GPIO10_ IN GPIO10_ IN 1 GPIO9_ IN GPIO9_ IN 0 GPIO8_ IN GPIO8_ IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[15:8]_IN
Function Not implemented When read, returns the status of the pin.
9.1.7 GPIO B Output Register (GPIOBOUT)
Location Read 7F1CH Write Reset 7 GPIO15_ OUT 1 6 GPIO14_ OUT 1 5 GPIO13_ OUT 1 4 GPIO12_ OUT 1 3 GPIO11_ OUT 1 2 GPIO10_ OUT 1 1 GPIO9_ OUT 1 0 GPIO8_ OUT 1
Symbol GPIO[15:8]_OUT
.
Function When written to, output data is updated. When read, returns previously written data.
9.1.8 GPIO B Function Select Register (GPIOBSEL)
Location Read 7F40H Write Reset 7 GPIO15_ SEL 0 6 GPIO14_ SEL 0 5 GPIO13_ SEL 0 4 GPIO12_ SEL 0 3 GPIO11_ SEL 0 2 GPIO10_ SEL 0 1 X 0 X
Symbol X GPIO15_SEL GPIO14_SEL GPIO13_SEL GPIO12_SEL GPIO11_SEL GPIO10_SEL
Function Not implemented Not defined 1: T2EX (Timer 2 external interrupt input) 0: GPIO15 function 1: SS2 (LPC Host interface status signal output 2) 0: GPIO14 function 1: SS1 (LPC Host interface status signal output 1) 0: GPIO13 function 1: SS0 (LPC Host interface status signal output 0) 0: GPIO12 function 1: KBRST#. (Keyboard Controller reset to CPU output) 0: GPIO11 function 1: ECLK (External clock input) 0: GPIO10 function
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Advance Information 9.1.9 LPC Status Signals Output Control Register (LPCSS)
Location Read 7FDFH Write Reset X X X X X 0 0 0 7 6 5 4 3 2 SSEL2 1 SSEL1 0 SSEL0
Symbol X SSEL[2:0] TABLE
Function Not implemented Not defined LPC Host status signals selection bits
9-1: LPC Host Status Signals as a Function of SSEL[2:0]
SS0# Output KBCSTS[IBF or OBF]1 KBCSTS[IBF or OBF] ECISTS[IBF or OBF] ECISTS[IBF or OBF] Mailbox Interrupt Status Mailbox Interrupt Status Reserved SS1# Output ECISTS[IBF or OBF]1 Mailbox Interrupt Status KBCSTS[IBF or OBF] Mailbox Interrupt Status KBCSTS[IBF or OBF] ECISTS[IBF or OBF] Reserved SS2# Output Mailbox Interrupt Status2 ECISTS[IBF or OBF] Mailbox Interrupt Status KBCSTS[IBF or OBF] ECISTS[IBF or OBF] KBCSTS[IBF or OBF] Reserved 000 001 010 011 100 101 110-111
SSEL2 SSEL1 SSEL0
1. Asserted when either IBF or OBF flag in the respective status register is set `1' (see also Sections 18.0, 20.0). 2. Asserted when either Host to 8051 or 8051 to Host interrupt is pending (see also Section 21.0).
9.1.10 GPIO C Direction Register (GPIOCDIR)
Location Read 7F1EH Write Reset 7 GPIO23_ DIR 0 6 X 5 X 4 X 3 X 2 X 1 X 0 X
Symbol X GPIO23_DIR
FunctionNot implemented Not defined GPIO direction control bit 1: Output 0: Input
9.1.11 GPIO C Input Register (GPIOCIN)1
Location Read 7F20H Write Reset 7 GPIO23_ IN GPIO23_ IN 6 GPIO22_ IN GPIO22_ IN 5 GPIO21_ IN GPIO21_ IN 4 GPIO20_ IN GPIO20_ IN 3 GPIO19_ IN GPIO19_ IN 2 GPIO18_ IN GPIO18_ IN 1 GPIO17_ IN GPIO17_ IN 0 GPIO16_ IN GPIO16_ IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[23:16]_IN
Function Not implemented When read, returns the status of the pin
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Advance Information 9.1.12 GPIO C Output Register (GPIOCOUT)
Location Read 7F1FH Write Reset 7 GPIO23_ OUT 1 6 GPIO22_ OUT 1 5 GPIO21_ OUT 1 4 GPIO20_ OUT 1 3 GPIO19_ OUT 1 2 GPIO18_ OUT 1 1 GPIO17_ OUT 1 0 GPIO16_ OUT 1
Symbol GPIO[23:16]_OUT
.
Function When written to, output data is updated. When read, returns previously written data.
9.1.13 GPIO C Function Select Register (GPIOCSEL)
Location Read 7FDCH Write Reset X 7 6 GPIO22_ SEL 0 5 GPIO21_ SEL 0 4 GPIO20_ SEL 0 3 GPIO19_ SEL 0 2 GPIO18_ SEL 0 1 GPIO17_ SEL 0 0 GPIO16_ SEL 0
Symbol X GPIO22_SEL GPIO21_SEL GPIO20_SEL GPIO19_SEL GPIO18_SEL GPIO17_SEL GPIO16_SEL
Function Not implemented Not defined 1: EC_SCI# (ACPI EC channel 0 interrupt output) 0: GPIO22 function 1: SMI# (System Management Interrupt output) 0: GPIO21 function 1: LED4 output 0: GPIO20 function 1: LED3 output 0: GPIO19 function 1: LED2 output 0: GPIO18 function 1: LED1 output 0: GPIO17 function 1: LED0 output 0: GPIO16 function
9.1.14 GPIO D Direction Register (GPIODDIR)
Location Read 7F22H Write Reset X X X X 7 6 5 4 3 GPIO27_ DIR 0 2 GPIO26_ DIR 0 1 GPIO25_ DIR 0 0 GPIO24_ DIR 0
Symbol X GPIO[27:24]_DIR
Function Not implemented Not defined GPIO direction control bit 1: Output 0: Input
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Advance Information 9.1.15 GPIO D Input Register (GPIODIN)1
Location Read 7F24H Write Reset 7 GPIO31_ IN GPIO31_ IN 6 GPIO30_ IN GPIO30_ IN 5 GPIO29_ IN GPIO29_ IN 4 GPIO28_ IN GPIO28_ IN 3 GPIO27_ IN GPIO27_ IN 2 GPIO26_ IN GPIO26_ IN 1 GPIO25_ IN GPIO25_ IN 0 GPIO24_ IN GPIO24_ IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[31:24]_IN
Function Not implemented When read, returns the status of the pin.
9.1.16 GPIO D Output Register (GPIODOUT)
Location Read 7F23H Write Reset 7 GPIO31_ OUT 1 6 GPIO30_ OUT 1 5 GPIO29_ OUT 1 4 GPIO28_ OUT 1 3 GPIO27_ OUT 1 2 GPIO26_ OUT 1 1 GPIO25_ OUT 1 0 GPIO24_ OUT 1
Symbol GPIO[31:24]_OUT
Function When written to, output data is updated. When read, returns previously written data.
9.1.17 GPIO D Function Select Register (GPIODSEL)
Location Read 7FDDH Write Reset 7 GPIO31_ SEL 0 6 GPIO30_ SEL 0 5 GPIO29_ SEL 0 4 GPIO28_ SEL 0 3 GPIO27_ SEL 0 2 GPIO26_ SEL 0 1 GPIO25_ SEL 0 0 GPIO24_ SEL 0
Symbol GPIO31_SEL GPIO30_SEL GPIO29_SEL GPIO28_SEL GPIO27_SEL GPIO26_SEL GPIO25_SEL GPIO24_SEL
Function 1: PSDAT1 (PS/2 channel 1 data pin) 0: GPIO31 function 1: PSCLK1 (PS/2 channel 1 clock pin) 0: GPIO30 function 1: PSDAT0 (PS/2 channel 0 data pin) 0: GPIO29 function 1: PSCLK0 (PS/2 channel 0 clock pin) 0: GPIO28 function 1: SDA2 (SMBus 2 data pin) 0: GPIO27 function 1: SCL2 (SMBus 2 clock pin) 0: GPIO26 function 1: FAN2 (Tachometer FAN 2 input) 0: GPIO25 function 1: FAN1 (Tachometer FAN 1 input) 0: GPIO24 function
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Advance Information 9.1.18 GPIO E Input Register (GPIOEIN)1
Location Read 7FA2H Write Reset 7 GPIO39_ IN GPIO39_ IN 6 GPIO38_ IN GPIO38_ IN 5 GPIO37_ IN GPIO37_ IN 4 GPIO36_ IN GPIO36_ IN 3 GPIO35_ IN GPIO35_ IN 2 GPIO34_ IN GPIO34_ IN 1 GPIO33_ IN GPIO33_ IN 0 GPIO32_ IN GPIO32_ IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[39:32]_IN
Function Not implemented When read, returns the status of the pin.
9.1.19 GPIO E Output Register (GPIOEOUT)
Location Read 7FA1H Write Reset 7 GPIO39_ OUT 1 6 GPIO38_ OUT 1 5 GPIO37_ OUT 1 4 GPIO36_ OUT 1 3 GPIO35_ OUT 1 2 GPIO34_ OUT 1 1 GPIO33_ OUT 1 0 GPIO32_ OUT 1
Symbol GPIO[39:32]_OUT
Function When written to, output data is updated. When read, returns previously written data.
9.1.20 GPIO E Function Select Register (GPIOESEL)
Location Read 7FDEH Write Reset 7 GPIO39_ SEL 1 6 GPIO38_ SEL 1 5 GPIO37_ SEL 0 4 GPIO36_ SEL 0 3 GPIO35_ SEL 0 2 GPIO34_ SEL 0 1 GPIO33_ SEL 0 0 GPIO32_ SEL 0
Symbol GPIO39_SEL GPIO38_SEL GPIO37_SEL GPIO36_SEL GPIO35_SEL GPIO34_SEL GPIO33_SEL GPIO32_SEL
Function 1: CLKRUN# function (PCI Clock Control signal) 0: GPIO39 function 1: LPCPD# input (LPC power down signal) 0: GPIO38 function 1: KSO15 output (Keyboard scan output 15) 0: GPIO37 function 1: KSO14 output (Keyboard scan output 14) 0: GPIO36 function 1: KSO13 output (Keyboard scan output 13) 0: GPIO35 function 1: KSO12 output (Keyboard scan output 12) 0: GPIO34 function 1: PSDAT2 (PS/2 channel 2 data pin) 0: GPIO33 function 1: PSCLK2 (PS/2 channel 2 clock pin) 0: GPIO32 function
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Advance Information 9.1.21 GPIO F Direction Register (GPIOFDIR)
Location Read 7FA3H Write Reset 7 GPIO47_ DIR 0 6 GPIO46_ DIR 0 5 X 4 X 3 X 2 GPIO42_ DIR 0 1 GPIO41_ DIR 0 0 X
Symbol X GPIO[47:46]_DIR
GPIO[42:41]_DIR
Function Not implemented Not defined GPIO direction control bit 1: Output 0: Input GPIO direction control bit 1: Output 0: Input
9.1.22 GPIO F Input Register (GPIOFIN)1
Location Read 7FA5H Write Reset 7 GPIO47_ IN GPIO47_ IN 6 GPIO46_ IN GPIO46_ IN 5 GPIO45_ IN GPIO45_ IN 4 GPIO44_ IN GPIO44_ IN 3 GPIO43_ IN GPIO43_ IN 2 GPIO42_ IN GPIO42_ IN 1 GPIO41_ IN GPIO41_ IN 0 GPIO40_ IN GPIO40_ IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[47:40]_IN
Function Not implemented When read, returns the status of the pin.
9.1.23 GPIO F Output Register (GPIOFOUT)
Location Read 7FA4H Write Reset 7 GPIO47_ OUT 1 6 GPIO46_ OUT 1 5 X 4 X 3 X 2 GPIO42_ OUT 1 1 GPIO41_ OUT 1 0 GPIO40_ OUT 1
Symbol X GPIO[47:40]_OUT
Function Not implemented Not defined When written to, output data is updated. When read, returns previously written data.
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Advance Information 9.1.24 GPIO F Function Select Register (GPIOFSEL)
Location Read 7FA6H Write Reset 7 GPIO47_ SEL 0 6 GPIO46_ SEL 0 5 GPIO45_ SEL 0 4 X 3 X 2 X 1 X 0 GPIO40_ SEL 0
Symbol X GPIO47_SEL GPIO46_SEL GPIO45_SEL GPIO40_SEL
Function Not implemented Not defined 1: T2 (Timer2 counter input or output) 0: GPIO47 function 1: T1 (Timer1 counter input or output) 0: GPIO46 function 1: T0 (Timer0 counter input) 0: GPI45 function 1: EC1_SCI (ACPI EC channel 1 interrupt output) 0: GPIO40 function
9.1.25 GPIO G Direction Register (GPIOGDIR)
Location Read 7F39H Write Reset 7 GPIO55_ DIR 0 6 GPIO54_ DIR 0 5 GPIO53_ DIR 0 4 GPIO52_ DIR 0 3 GPIO51_ DIR 0 2 GPIO50_ DIR 0 1 GPIO49_ DIR 0 0 GPIO48_ DIR 0
Symbol GPIO[55:48]_DIR
Function GPIO direction control bit 1: Output 0: Input
9.1.26 GPIO G Input Register (GPIOGIN)1
Location Read 7F3BH Write Reset 7 GPIO55_ IN GPIO55_ IN 6 GPIO54_ IN GPIO54_ IN 5 GPIO53_ IN GPIO53_ IN 4 GPIO52_ IN GPIO52_ IN 3 GPIO51_ IN GPIO51_ IN 2 GPIO50_ IN GPIO50_ IN 1 GPIO49_ IN GPIO49_ IN 0 GPIO48_ IN GPIO48_ IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[55:48]_IN
Function Not implemented When read, returns the status of the pin.
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Advance Information 9.1.27 GPIO G Output Register (GPIOGOUT)
Location Read 7F3AH Write Reset 7 GPIO55_ OUT 1 6 GPIO54_ OUT 1 5 GPIO53_ OUT 1 4 GPIO52_ OUT 1 3 GPIO51_ OUT 1 2 GPIO50_ OUT 1 1 GPIO49_ OUT 1 0 GPIO48_ OUT 1
Symbol GPIO[55:48]_OUT
.
Function When written to, output data is updated. When read, returns previously written data.
9.1.28 GPIO G Function Select Register (GPIOGSEL)
Location Read 7F3CH Write Reset X 7 6 GPIO54_ SEL 0 5 GPIO53_ SEL 0 4 GPIO52_ SEL 0 3 GPIO51_ SEL 0 2 GPIO50_ SEL 0 1 GPIO49_ SEL 0 0 GPIO48_ SEL 0
Symbol X GPIO54_SEL GPIO53_SEL GPIO52_SEL GPIO51_SEL GPIO50_SEL GPIO49_SEL GPIO48_SEL
Function Not implemented Not defined 1: SCL1 (SMBus 1 clock)/TXD (UART transmit output) selected by UART_SM bit 0: GPIO54 function 1: SDA1 (SMBus 1 data)/RXD (UART receive input) selected by UART_SM bit 0: GPIO53 function 1: SCL0 (SMBus 0 clock pin) 0: GPIO52 function 1: SDA0 (SMBus 0 data pin) 0: GPIO51 function 1: 32KCLKOUT (32.768KHz clock signal output) 0: GPIO50 function. 1: CLKOUT (8051 core clock output) 0: GPIO49 function. 1: WDOGOUT (Watchdog timer output) 0: GPIO48 function.
9.1.29 GPIO H Direction Register (GPIOHDIR)
Location Read 7FE0H Write Reset 7 GPIO63_ DIR 0 6 GPIO62_ DIR 0 5 GPIO61_ DIR 0 4 GPIO60_ DIR 0 3 GPIO59_ DIR 0 2 GPIO58_ DIR 0 1 GPIO57_ DIR 0 0 GPIO56_ DIR 0
Symbol GPIO[63:56]_DIR
Function GPIO direction control bit 1: Output 0: Input
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Advance Information 9.1.30 GPIO H Input Register (GPIOHIN)1
Location Read 7FE2H Write Reset 7 GPIO63_ IN GPIO63_ IN 6 GPIO62_ IN GPIO62_ IN 5 GPIO61_ N GPIO61_ N 4 GPIO60_ IN GPIO60_ IN 3 GPIO59_ IN GPIO59_ IN 2 GPIO58_ IN GPIO58_ IN 1 GPIO57_ IN GPIO57_ IN 0 GPIO56_ IN GPIO56_ IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
= Unimplemented
Symbol GPIO[63:56]_IN
Function Not implemented When read, returns the status of the pin.
9.1.31 GPIO H Output Register (GPIOHOUT)
Location Read 7FE1H Write Reset 7 GPIO63_ OUT 1 6 GPIO62_ OUT 1 5 GPIO61_ OUT 1 4 GPIO60_ OUT 1 3 GPIO59_ OUT 1 2 GPIO58_ OUT 1 1 GPIO57_ OUT 1 0 GPIO56_ OUT 1
Symbol GPIO[63:56]_OUT
Function When written to, output data is updated. When read, returns previously written data.
9.1.32 GPIO HL Open-Drain/Push-Pull Section Register (GPIOHLOD)
Location Read 7FABH Write Reset 7 GPIO63_ OD 0 6 GPIO62_ OD 0 5 GPIO61_ OD 0 4 GPIO60_ OD 0 3 GPIO91_ OD 0 2 GPIO90_ OD 0 1 GPIO89_ OD 0 0 GPIO88_ OD 0
Symbol GPIO[63:60]_OD
GPIO[91:88]_OD
Function GPIO output buffer configuration control bit 1: Open-Drain configuration 0: Push-Pull configuration GPIO output buffer configuration control bit 1: Open-Drain configuration 0: Push-Pull configuration
9.1.33 GPIO I Direction Register (GPIOIDIR)
Location Read 7FE3H Write Reset 7 GPIO71_ DIR 0 6 GPIO70_ DIR 0 5 GPIO69_ DIR 0 4 GPIO68_ DIR 0 3 GPIO67_ DIR 0 2 GPIO66_ DIR 0 1 GPIO65_ DIR 0 0 GPIO64_ DIR 0
Symbol GPIO[71:64]_DIR
Function GPIO direction control bit 1: Output 0: Input
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Advance Information 9.1.34 GPIO I Input Register (GPIOIIN)1
Location Read 7FE5H Write Reset 7 GPIO71_ IN GPIO71_ IN 6 GPIO70_ IN GPIO70_ IN 5 GPIO69_ IN GPIO69_ IN 4 GPIO68_ IN GPIO68_ IN 3 GPIO67_ IN GPIO67_ IN 2 GPIO66_ IN GPIO66_ IN 1 GPIO65_ IN GPIO65_ IN 0 GPIO64_ IN GPIO64_ IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[67:64]_IN GPIO[71:68]_IN
Function Not implemented When read, returns the status of the pin. When read, returns the status of the pin in normal GPIO mode only.
9.1.35 GPIO I Output Register (GPIOIOUT)
Location Read 7FE4H Write Reset 7 GPIO71_ OUT 1 6 GPIO70_ OUT 1 5 GPIO69_ OUT 1 4 GPIO68_ OUT 1 3 GPIO67_ OUT 1 2 GPIO66_ OUT 1 1 GPIO65_ OUT 1 0 GPIO64_ OUT 1
Symbol GPIO[71:64]_OUT
Function When written to, output data is updated. When read, returns previously written data
9.1.36 GPIO I Function Select Register (GPIOISEL)
Location Read 7FF0H Write Reset 7 GPIO71_ SEL 0 6 GPIO70_ SEL 0 5 GPIO69_ SEL 0 4 GPIO68_ SEL 0 3 X 2 X 1 X 0 X
Symbol X GPIO71_SEL GPIO70_SEL GPIO69_SEL GPIO68_SEL
Function Not implemented Not Defined 1: DAC3 (Digital to Analog converter channel 3 output) 0: GPIO71 function 1: DAC2 (Digital to Analog converter channel 2 output) 0: GPIO70 function 1: DAC1 (Digital to Analog converter channel 1 output) 0: GPIO71 function 1: DAC0 (Digital to Analog converter channel 0 output) 0: GPIO70 function
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Advance Information 9.1.37 GPIO I Open-Drain/Push-Pull Section Register (GPIOIOD)
Location Read 7FACH Write Reset 7 GPIO71_ OD 0 6 GPIO70_ OD 0 5 GPIO69_ OD 0 4 GPIO68_ OD 0 3 GPIO67_ OD 0 2 GPIO66_ OD 0 1 GPIO65_ OD 0 0 GPIO64_ OD 0
Symbol GPIO[71:64]_OD
Function GPIO output buffer configuration control bit. 1: Open-Drain configuration 0: Push-Pull configuration
9.1.38 GPIO J Direction Register (GPIOJDIR)
Location Read 7FE6H Write Reset 7 GPIO79_ DIR 0 6 GPIO78_ DIR 0 5 GPIO77_ DIR 0 4 GPIO76_ DIR 0 3 GPIO75_ DIR 0 2 GPIO74_ DIR 0 1 GPIO73_ DIR 0 0 GPIO72_ DIR 0
Symbol GPIO[79:72]_DIR
Function GPIO direction control bit 1: Output 0: Input
9.1.39 GPIO J Input Register (GPIOJIN)1
Location Read 7FE8H Write Reset 7 GPIO79_ IN GPIO79_ IN 6 GPIO78_ IN GPIO78_ IN 5 GPIO77_ IN GPIO77_ IN 4 GPIO76_ IN GPIO76_ IN 3 GPIO75_ IN GPIO75_ IN 2 GPIO74_ IN GPIO74_ IN 1 GPIO73_ IN GPIO73_ IN 0 GPIO72_ IN GPIO72_ IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[79:72]_IN
Function Not implemented When read, returns the status of the pin in normal GPIO mode only.
9.1.40 GPIO J Output Register (GPIOJOUT)
Location Read 7FE7H Write Reset 7 GPIO79_ OUT 1 6 GPIO78_ OUT 1 5 GPIO77_ OUT 1 4 GPIO76_ OUT 1 3 GPIO75_ OUT 1 2 GPIO74_ OUT 1 1 GPIO73_ OUT 1 0 GPIO72_ OUT 1
Symbol GPIO[79:72]_OUT
Function When written to, output data is updated. When read, returns previously written data.
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Advance Information 9.1.41 GPIO J Function Select Register (GPIOJSEL)
Location Read 7FF5H Write Reset 7 GPIO79_ SEL 0 6 GPIO78_ SEL 0 5 GPIO77_ SEL 0 4 GPIO76_ SEL 0 3 GPIO75_ SEL 0 2 GPIO74_ SEL 0 1 GPIO73_ SEL 0 0 GPIO72_ SEL 0
Symbol GPIO[79:72]_SEL
Function 1: ACH[0:7] Analog to Digital converter channel 0 to 7 0: GPIO[79:72] function
9.1.42 GPIO J Open-Drain/Push-Pull Section Register (GPIOJOD)
Location Read 7FADH Write Reset 7 GPIO79_ OD 0 6 GPIO78_ OD 0 5 GPIO77_ OD 0 4 GPIO76_ OD 0 3 GPIO75_ OD 0 2 GPIO74_ OD 0 1 GPIO73_ OD 0 0 GPIO72_ OD 0
Symbol GPIO[79:72]_OD
Function GPIO output buffer configuration control bit 1: Open-Drain configuration 0: Push-Pull configuration
9.1.43 GPIO K Direction Register (GPIOKDIR)
Location Read 7FE9H Write Reset 7 GPIO87_ DIR 0 6 GPIO86_ DIR 0 5 GPIO85_ DIR 0 4 GPIO84_ DIR 0 3 GPIO83_ DIR 0 2 GPIO82_ DIR 0 1 GPIO81_ DIR 0 0 GPIO80_ DIR 0
Symbol GPIO[87:80]_DIR
Function GPIO direction control bit 1: Output 0: Input
9.1.44 GPIO K Input Register (GPIOKIN)1
Location Read 7FEBH Write Reset 7 GPIO87_ IN GPIO87_ IN 6 GPIO86_ IN GPIO86_ IN 5 GPIO85_ IN GPIO85_ IN 4 GPIO84_ IN GPIO84_ IN 3 GPIO83_ IN GPIO83_ IN 2 GPIO82_ IN GPIO82_ IN 1 GPIO81_ IN GPIO81_ IN 0 GPIO80_ IN GPIO80_ IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[87:80]_IN
Function Not implemented When read, returns the status of the pin.
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Advance Information 9.1.45 GPIO K Output Register (GPIOKOUT)
Location Read 7FEAH Write Reset 7 GPIO87_ OUT 1 6 GPIO86_ OUT 1 5 GPIO85_ OUT 1 4 GPIO84_ OUT 1 3 GPIO83_ OUT 1 2 GPIO82_ OUT 1 1 GPIO81_ OUT 1 0 GPIO80_ OUT 1
Function When written to, output data is updated. When read, returns previously written data. 9.1.46 GPIO K Pull-up Control Register (GPIOKPU)
Location Read 7FB7H Write Reset X X 7 6 5 GPIO85 PU 0 4 GPIO84 PU 0 3 GPIO83 PU 0 2 GPIO82 PU 0 1 GPIO81 PU 0 0 GPIO80 PU 0
Symbol GPIO[87:80]_OUT
Symbol X GPIO[85:80]PU
Function Not implemented Not defined GPIO Internal Pull-up control bit 1: Enable Internal Pull-up 0: Disable Internal Pull-up
9.1.47 GPIO L Direction Register (GPIOLDIR)
Location Read 7FA7H Write Reset 7 GPIO95_ DIR 0 6 GPIO94_ DIR 0 5 GPIO93_ DIR 0 4 GPIO92_ DIR 0 3 GPIO91_ DIR 0 2 GPIO90_ DIR 0 1 GPIO89_ DIR 0 0 GPIO88_ DIR 0
Symbol GPIO[95:88]_DIR
Function GPIO direction control bit 1: Output 0: Input When GPIO[95:94]_DIR=0, GPIO[95:94] are inputs with internal pull-ups enabled
9.1.48 GPIO L Input Register (GPIOLIN)1
Location Read 7FA9H Write Reset 7 GPIO95_ IN GPIO95_ IN 6 GPIO94_ IN GPIO94_ IN 5 GPIO93_ IN GPIO93_ IN 4 GPIO92_ IN GPIO92_ IN 3 GPIO91_ IN GPIO91_ IN 2 GPIO90_ IN GPIO90_ IN 1 GPIO89_ IN GPIO89_ IN 0 GPIO88_ IN GPIO88_ IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[95:88]_IN
Function Not implemented When read, returns the status of the pin.
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Advance Information 9.1.49 GPIO L Output Register (GPIOLOUT)
Location Read 7FA8H Write Reset 7 GPIO95_ OUT 1 6 GPIO94_ OUT 1 5 GPIO93_ OUT 1 4 GPIO92_ OUT 1 3 GPIO91_ OUT 1 2 GPIO90_ OUT 1 1 GPIO89_ OUT 1 0 GPIO88_ OUT 1
Symbol GPIO[95:88]_OUT
Function When written to, output data is updated. When read, returns previously written data.
9.1.50 GPIO M Pullup Control Register (GPIOMPU)
Location Read 7F5BH Write Reset 7 GPIO103 _PU 0 6 GPIO102 _PU 0 5 GPIO101 _PU 0 4 GPIO100 _PU 0 3 GPIO99_ PU 0 2 GPIO98_ PU 0 1 GPIO97_ PU 0 0 GPIO96_ PU 0
Symbol GPIO[103:96]_PU
Function GPIO Internal Pullup control bit 1: Disable Internal Pullup 0: Enable Internal Pullup
9.1.51 GPIO M Input Register (GPIOMIN)1
Location Read 7F6BH Write Reset 7 GPIO103_ IN GPIO103_ IN 6 GPIO102_ IN GPIO102_ IN 5 GPIO101_ IN GPIO101_ IN 4 GPIO100_ IN GPIO100_ IN 3 GPIO99_ IN GPIO99_ IN 2 GPIO98_ IN GPIO98_ IN 1 GPIO97_ IN GPIO97_ IN 0 GPIO96_ IN GPIO96_ IN
1. When using an open drain pin as an input, output data must be specified as `1'`1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[103:96]_IN
Function Not implemented When read, returns the status of the pin.
9.1.52 GPIO M Output Register (GPIOMOUT)
Location Read 7F30H Write Reset 7 GPIO103 _OUT 1 6 GPIO102 _OUT 1 5 GPIO101 _OUT 1 4 GPIO100 _OUT 1 3 GPIO99_ OUT 1 2 GPIO98_ OUT 1 1 GPIO97_ OUT 1 0 GPIO96_ OUT 1
Symbol GPIO[103:96]_OUT
Function When written to, output data is updated (see Table 9-2 below). When read, returns previously written data.
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Advance Information 9.1.53 GPIO M Open-Drain/Push-Pull Section Register (GPIOMOD)
Location Read 7FF6H Write Reset 7 GPIO103 _OD 0 6 GPIO102 _OD 0 5 GPIO101 _OD 0 4 GPIO100 _OD 0 3 GPIO99_ OD 0 2 GPIO98_ OD 0 1 GPIO97_ OD 0 0 GPIO96_ OD 0
Symbol GPIO[103:96]_OD
Function GPIO output buffer configuration control bit (see Table 9-2 below)
9.1.54 GPIO N Pullup Control Register (GPIONPU)
Location Read 7F83H Write Reset 7 GPIO111 _PU 0 6 GPIO110 _PU 0 5 GPIO109 _PU 0 4 GPIO108 _PU 0 3 GPIO107 _PU 0 2 GPIO106 _PU 0 1 GPIO105 _PU 0 0 GPIO104 _PU 0
Symbol GPIO[111:104]_PU
Function GPIO Internal Pullup control bit 1: Disable Internal Pullup 0: Enable Internal Pullup
9.1.55 GPIO N Input Register (GPIONIN)1
Location Read 7F84H Write Reset 7 GPIO111 _IN GPIO111 _IN 6 GPIO110 _IN GPIO110 _IN 5 GPIO109 _IN GPIO109 _IN 4 GPIO108 _IN GPIO108 _IN 3 GPIO107 _IN GPIO107 _IN 2 GPIO106 _IN GPIO106 _IN 1 GPIO105 _IN GPIO105 _IN 0 GPIO104 _IN GPIO104 _IN
1. When using an open drain pin as an input, output data must be specified as `1'. However, specifying output data as `0' when using an open drain pin as an input will damage the part.
Symbol GPIO[111:104]_IN
Function Not implemented When read, returns the status of the pin.
9.1.56 GPIO N Output Register (GPIONOUT)
Location Read 7F82H Write Reset 7 GPIO111 _OUT 1 6 GPIO110 _OUT 1 5 GPIO109 _OUT 1 4 GPIO108 _OUT 1 3 GPIO107 _OUT 1 2 GPIO106 _OUT 1 1 GPIO105 _OUT 1 0 GPIO104 _OUT 1
Symbol GPIO[111:104]_OUT
Function When written to, output data is updated (see Table 9-2). When read, returns previously written data.
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Advance Information 9.1.57 GPIO N Open-Drain/Push-Pull Section Register (GPIONOD)
Location Read 7FFCH Write Reset 7 GPIO111 _OD 0 6 GPIO110 _OD 0 5 GPIO109 _OD 0 4 GPIO108 _OD 0 3 GPIO107 _OD 0 2 GPIO106 _OD 0 1 GPIO105 _OD 0 0 GPIO104 _OD 0
Symbol GPIO[111:104]_OD TABLE
Function GPIO output buffer configuration control bit (see Table 9-2 below)
9-2: GPIO96-GPIO111 Input/Output configuration control
GPIOn_OD 0 0 1 1 GPIOn_OUT 0 1 0 1 Input/Output Output `0' Input / Output `1' open drain Output `0' Output `1' push pull
T9-2.0 1320
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Advance Information
10.0 TIMERS/COUNTERS, WATCHDOG TIMER AND PWM 10.1 Timers: T0, T1, T2
The SST79LF008 device has three 16-bit registers that can be used as either timers or event counters. The three timers/counters are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2). Each is designated a pair of 8-bit registers in the Special Function Registers (SFRs). The pair of registers consists of a most significant (high) byte and least significant (low) byte. The respective registers are TL0, TH0, TL1, TH1, TL2, and TH2. See Table 10-4. Timer 2 also has the capture registers RCAP2L and RCAP2H. See Table 10-4. ferent. Table 10-1 and Table 10-2 provide the examples of TMOD values to be used to select operation modes for timers T1 and T0. 10.2.1.1 Mode 0 In Mode 0 each timer is configured as a 13-bit timer, which includes 8-bit counter (TH1/TH0) and a 5-bit prescaler (lower 5 bits of TL1/TL0). As the count overflows from all 1s to all 0s, the counter continues to count, and the respective timer overflow flag TF1/TF0 is set. 10.2.1.2 Mode 1 Mode 1 is similar to Mode 0, with the exception that each timer uses full 16-bit counter. The clock is applied to the combined high and low timer registers TH1:TL1/TH0:TL0. 10.2.1.3 Mode 2 In Mode 2 each timer is configured as an 8-bit counter with automatic reload. Timer 1 uses TL1 register as a counter; when overflow occurs, bit TF1 is set, and TL1 is reloaded with the contents of register TH1. Timer 0 uses TL0 register as a counter; when overflow occurs, bit TF0 is set, and TL0 is reloaded with the contents of register TH0. The reload does not modify TH1/TH0 value. 10.2.1.4 Mode 3 Timer 1 in Mode 3 is halted and holds its count. Timer 0 in Mode 3 is divided into two separate 8-bit counters TL0 and TH0. Timer 0 control bits: C/T#_T0, TR0, and TF0 are dedicated to TL0 operations only. Timer 1 control bits: TR1 and TF1 are dedicated to TH0 operations only, and TH0 is forced into timer mode which uses CCLK divided by 12 as a clock source.
10.2 Timer Operations
Refer to Section 10.3 for full description of the TCON, TMOD, T2CON and T2MOD registers that control timer operations. 10.2.1 Timer 1 and Timer 0 Timer 1 and Timer 0 operations are controlled by TMOD and TCON registers. Each timer can be configured to operate either as a timer or event counter depending on the value of the bits C/T#_T1 and C/T_/T0 in TMOD register. The clock source for timer function is 8051 core clock CCLK divided by 12. The clock source for the event counter function is either the T1 or T0 input pin respectively, or crystal oscillator clock XCLK as selected by CLKCON register (active falling edge for any source). Both the T1 and T0 timers count up. Each timer can be turned ON by setting, or turned OFF by clearing, the TR1/TR0 bit in TCON register. There are four operating modes available in either timer or counter operations. In Modes 0, 1 and 2 both T0 and T1 operate similarly. In Mode 3, T0 and T1 operations are difTABLE 10-1: Timer 0 Operating Modes
Mode Used as Timer 0 1 2 3 Used as Counter 0
Function 13-bit Timer 16-bit Timer 8-bit Auto-Reload Two 8-bit Timers 13-bit Counter 8-bit Counter TH0 with TL0 as 5-bit prescaler 16-bit Counter 8-bit Auto-Reload Two 8-bit Counters
TMOD1 00H 01H 02H 03H 04H
1 2 3
1. The Timer is turned ON/OFF by setting/clearing bit TR0.
05H 06H 07H
T10-1.0 1320
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Advance Information TABLE 10-2: Timer 1 Operating Modes
Mode Used as Timer 0 1 2 3 Used as Counter 0 1 2 3
1. The Timer is turned ON/OFF by setting/clearing bit TR1.
Function 13-bit Timer 16-bit Timer 8-bit Auto-Reload Stopped 13-bit Counter 8-bit Counter TH1 with TL1 as 5-bit prescaler 16-bit Counter 8-bit Auto-Reload Not Available
TMOD1 00H 10H 20H 30H 40H 50H 60H T10-2.0 1320
10.2.2 Timer 2 Similar to Timer 1 and 0, Timer 2 can operate either as a timer or as an event counter, depending on the value of bit C/T2# in T2CON register. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. Refer to Table 10-3 examples of the respective settings. 10.2.2.1 16-bit Timer/Counter Capture Mode In the capture mode, the EXEN2 bit in T2CON selects one of two options. If EXEN2 bit is cleared to 0, then Timer 2 is a 16-bit timer/counter. When the timer/counter overflow occurs, Timer 2 overflow bit TF2 will be set. If EXEN2 bit is set to 1, then Timer 2 operates the same way, but in addition a falling edge on the external input T2EX causes the current value in the Timer 2 registers TL2 and TH2 to be captured into the RCAP2L and RCAP2H registers respectively. The T2EX falling edge also sets the EXF2 bit in T2CON. Either TF2 or EXF2 flags can generate Timer 2 interrupt to 8051. TABLE 10-3: Timer 2 Operating Modes
10.2.2.2 16-bit Timer/Counter Auto-reload Mode In the auto-reload mode, the EXEN2 bit in T2CON also selects one of two options. If EXEN2 is cleared to 0, then when the 16-bit timer/counter overflow occurs. TF2 bit is set, and Timer 2 registers are reloaded with the contents of the RCAP2L and RCAP2H registers. If EXEN2 is set to 1, then Timer 2 operates the same way as above, but, in addition a falling edge on the external input, T2EX also triggers the counter reload and sets EXF2 bit. Either TF2 or EXF2 flags can generate Timer 2 interrupt to 8051. 10.2.2.3 Baud Rate Generator Mode When RCLK or TCLK bit is set to 1, T2 output signal determines UART baud rates for receive and/or transmit as described in Section 11.0. This mode is similar to autoreload mode with the following exceptions: TF2 flag is not set on overflow, and T2EX falling edge does not cause a reload.
T2CON1 Mode Used as Timer 16-bit Auto Reload 16-bit Capture Baud rate generator Receive and Transmit Receive only Transmit only Used as Counter 16-bit Auto Reload 16-bit Capture Internal Control2 00H 01H 30H 20H 10H 02H 03H External Control3 08H 09H 38H 28H 18H 0AH 0BH
T10-3.0 1320
1. The Timer is turned ON/OFF by setting/clearing bit TR2. 2. Capture/Reload occurs only on timer or counter overflow. 3. Capture/Reload occurs on timer or counter overflow and a 1 to 0 transition on T2EX pin except when Timer 2 is used in the baud rate generating mode. The GPIO15 pin must be set as T2EX.
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Advance Information
10.3 Timers/Counters SFRs
TABLE 10-4: Timer/Counters SFRs
Symbol TMOD Description Timer/Counter Mode Control Timer/Counter Control Timer 0 MSB Timer 0 LSB Timer 1 MSB Timer 1 LSB Timer / Counter 2 Control Timer 2 Mode Control Timer 2 MSB Timer 2 LSB Timer 2 Capture MSB Timer 2 Capture LSB Direct Address 89H GATE _T1 88H 8CH 8AH 8DH 8BH C8H C9H CDH CCH CBH CAH TF2 EXF2 RCLK TF1 Symbol MSB Timer 1 Control bits C/ T#_T1 TR1 M1_ T1 TF0 M0_ T1 TR0 GATE _T0 IE1 Timer 0 Control bits C/ T#_T0 IT1 M1_ T0 IE0 M0_ T0 IT0 00H 00H 00H 00H 00H TR2 T1OE C/T2# T2OE CP/ RL2# DCEN 00H X0H 00H 00H 00H 00H
T10-4.0 1320
LSB
RESET Value 00H
TCON1 TH0 TL0 TH1 TL1 T2CON1 T2MOD# TH2 TL2 RCAP2H RCAP2L
TH0[7:0] TL0[7:0] TH1[7:0] TL1[7:0] TCLK EXEN 2 -
TH2[7:0] TL2[7:0] RCAP2H[7:0] RCAP2L[7:0]
1. Bit x Addressable SFRs -8.0 555
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Advance Information 10.3.1 Timer / Counter Control Register (TCON)
Location Read 88H Write Reset 0 0 0 0 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 0 2 IT1 0 1 IE0 0 0 IT0 0
Symbol TF1
TR1 TF0
TR0 IE1
IT1 IE0
IT0
Function Not implemented Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt service routine, or it can be cleared in software. Timer 1 run control bit. Set/cleared by software to turn on/off Timer/Counter Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt service routine, or can be cleared in software. Timer 0 run control bit. Set/cleared by software to turn on/off Timer/Counter Interrupt INT1 request flag This is read only bit equal to the INT1 signal (see Figure 8-1 for INT1 signal sources) Interrupt 1 type control bit. Always cleared. 0: INT1 is a level triggered interrupt Interrupt INT0 request flag This is a read only bit equal to the INT0 signal (see Figure 8-1 for INT0 signal sources) Interrupt 0 type control bit. Always cleared. 0: INT0 is a level triggered interrupt
10.3.2 Timer / Counter Mode Register (TMOD)
Location Read 89H Write Reset 7 GATE_T1 0 6 C/T#_T1 0 5 M1_T1 0 4 M0_T1 0 3 GATE_T0 0 2 C/T#_T0 0 1 M1_T0 0 0 M0_T0 0
Symbol GATE_T1 C/T#_T1
M1_T1 M0_T1 GATE_T0 C/T#_T0
M1_T0 M0_T0
Function Not implemented Timer 1 gating control bit. Always cleared. 0: Gate function is disabled and Timer 1 is controlled by TR1 bit only. Timer or Counter Selector bit (Timer 1). 1: Counter operation (input clock is selected by CLKCON register). 0: Timer operation (input clock frequency is FCCLK/12). Mode bit 1 for T1. Mode bit 0 for T1. Timer 0 gating control bit. Always cleared. 0: Gate function is disabled and Timer 0 is controlled by TR0 bit only. Timer or Counter Selector bit (Timer 0) 1: Counter operation (input clock is selected by CLKCON register). 0: Timer operation (input clock frequency is FCCLK/12). Mode bit 1 for T0. Mode bit 0 for T0.
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Advance Information TABLE 10-5: Timer Operating Mode as a Function of Mode Bits
M1_Tn1 0 0 1 M0_Tn1 0 1 0 Mode 0 1 2 Operating mode 13-bit Timer Mode. 8-bit Timer/Counter THn with TLn as 5-bit prescaler. 16-bit Timer Mode. THn and TLn are cascaded into 16-bit Timer/Counter with no prescaler. 8-bit Auto Reload Mode. THn holds a value, which has to be reloaded into 8-bit auto-reload Timer/Counter TL1 each time it overflows. Timer/Counter 1 is stopped. TL0 is an 8-bit Timer/Counter controlled by the Timer 0 control bits. TH0 is an 8-bit Timer only controlled by Timer 1 control bits.
T10-5.1320
1 1
1 1
3 (T1) 3 (T0)
1. n=0,1
10.3.3 Timer/Counter 2 Control Register (T2CON)
Location Read C8H Write Reset 0 0 0 0 0 0 0 0 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2#
Symbol TF2
EXF2
RCLK
TCLK
EXEN2
TR2 C/T2#
CP/RL2#
Function Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set in baud rate generator mode (when RCLK or TCLK = 1) and in clock output mode (when T20E = 1 and C/T2# = 0). Timer 2 external flag set when either a capture or reload is caused by a falling edge on T2EX and EXEN2 = 1, and must be cleared by software. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Receive clock flag. When set, causes the UART to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock flag. When set, causes the UART to use Timer 2 overflow pulses to transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflow to be used for the transmit clock. Timer 2 external enable control bit. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the UART. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. A logic `1' starts the Timer 2. A logic `0' stops Timer 2 Timer or counter select (Timer 2) 1: External event counter (T2 input pin falling edge-triggered) 0: Internal timer input clock frequency is FCCLK/12 when RCLK = 0 and TCLK = 0 input clock frequency is FCCLK/2 when RCLK = 1 or TCLK = 1 Capture/Reload flag. When set, captures occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads occur either when Timer 2 overflows or with negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
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Advance Information 10.3.4 Timer/Counter 2 Mode Control (T2MOD)
Location Read C9H Write Reset 7 X 6 X 5 X 4 X 3 X 2 T1OE 0 1 T2OE 0 0 DCEN 0
Symbol X T1OE
T2OE
DCEN
Function Not implemented Not defined Timer 1 Output Enable bit 1: Enable Timer 1 output. Bit C/T#_T1 must be cleared. A 50% duty cycle will be output. T1OE bit does not affect T1 overflow interrupt 0: Disable Timer 1 output Timer 2 Output Enable bit 1: Enable Timer 2 output. Bit C/T2# must be cleared. A 50% duty cycle will be output. If T2OE = 1, TF2 overflow flag will not be set on Timer 2 roll-over, and T2 overflow interrupt will not be generated. If T2OE = 0, TF2 overflow interrupt is not affected. 0: Disable Timer 2 output Timer 2 Down Count Enable bit 1: Timer 2 can be configured as an up or down counter. The T2EX pin controls the count direction. A logic `1' at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH-to-0000H transition and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into timer registers TH2 and TL2 respectively. Logic `0' at T2EX makes Timer 2 count down. In this case the timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows. This bit can be used as a 17th bit of resolution if desired. In this operating mode, EXF2 does not generate an interrupt. 0: Timer 2 is configured as up counter only
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Advance Information
10.4 Watchdog Timer (WDT)
A watchdog timer (WDT) is a hardware timer that offers protection against software and/or hardware deadlock during normal operation. When the WDT is enabled, it will generate a chip reset or interrupt if the user program does not reload the WDTDAT register within a specified time interval. The frequency of the XCLK clock source for the WDT is 32.768 KHz. The WDT has a 9-bit prescaler, which makes the watchdog timer resolution equal to approximately 16.0ms. Hence, the 8-bit watchdog counter provides a watchdog time interval from 16ms to 4 seconds. Both the watchdog counter and the prescaler are reset when the unit is disabled.
XCLK
9-bit Hardware Prescaler
Loadable 8-bit Down Counter
1245 WDTimer.0
FIGURE
10-1: Watchdog Timer one 32KHz clock cycle. When WDT reset is disabled, and WDT interrupt is enabled (WDTMSK = 1), this output will stay asserted until the interrupt is cleared; WDT will stay in underflow state and will not wrap around. When data register is reloaded or WDT is disabled by clearing WDTEN = 0, the underflow state is exited. On exit from underflow state WDT interrupt is cleared, and WDT output is deasserted. It is possible to prevent both WDT reset and WDT interrupt from happening when WDTRSTEN = WDTMSK = 0. There are two methods to disable the WDT operation at run time: (1) clear the WDT enable bit directly, or (2) reload the WDT data register with 00H, which will automatically clear WDT enable bit.
After POR, BOR, External reset, WDT reset, or aLPC Soft reset the WDT is disabled. The WDT commences counting down from the loaded WDT data value as soon as enable bit WDTEN in WDTCSR register is set. Once activated, the WDT must be reloaded periodically in software before the programmed WDT interval expires. Otherwise, the WDT will underflow and a WDT reset or interrupt will be generated. WDT reset is controlled by the WDTRSTEN bit in RSTCON register, and WDT interrupt is controlled by the WDTMSK bit in INTSRCAMSK register. Both WDT reset and WDT interrupt will generate an output signal on GPIO48 if it is selected as WDT output pin. When WDT reset is enabled (WDTRSTEN = 1), this output will be asserted for
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Advance Information 10.4.1 Watchdog Timer MMCRs 10.4.1.1 Watchdog Timer Control / Status Register (WDTCSR)
Location Read 7F37H Write Reset 7 WDTSTOPEN 0 6 X 5 X 4 X 3 X 2 X 1 WDTEN 0 0 WLE 0
Symbol X WDTSTOPEN
WDTEN
WLE
Function Not implemented Not defined WDT Power Down mode operation control bit 1: WDT keeps running when 8051 enters into Power Down mode provided WDT is enabled. 0: WDT is stopped when 8051 enters into Power Down mode. WDT automatically resumes running after Power Down exit staring with the default value 0FFH. WDT Enable bit. Set by firmware to enable (start) the WDT. Automatically cleared when loading 00H to WDTDAT register. 1: Enable WDT operation 0: Disable WDT operation Watchdog Load Enable bit. Set by firmware to enable writing to the WDTDAT register. Automatically cleared when writing any data to the WDTDAT register. 1: Enable writes to WDTDAT register (WDT is reloaded) 0: Disable writes to the WDTDAT register (write is ignored).
10.4.1.2 Watchdog Data Register (WDTDAT)
Location Read 7F38H Write Reset 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 WDTDAT7 WDTDAT6 WDTDAT5 WDTDAT4 WDTDAT3 WDTDAT2 WDTDAT1 WDTDAT0
Function WDT data When written to and WLE = 1, the WDT timer is initialized (counter is loaded with the respective data byte, and prescaler is reset). When read, it will return the current value. The watchdog timer (WDT) must be reloaded within the periods that are shorter than the programmed watchdog interval; otherwise the WDT will underflow. Note: Recommended WDT start software sequence: set WLE = 1 first, next load WDTDAT, and finally set WDTEN = 1
Symbol WDTDAT[7:0]
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Advance Information
10.5 Hibernation Timer
SST79LF008 has a hibernation timer which allows for hibernation time of up to 127.5 minutes in 30-second intervals. The XCLK clock source for the hibernation timer is derived from a 32.768 KHz crystal. In order to generate a 30-second time interval, there is a 20-bit prescaler which counts up from 0 to F0000H and then wraps around to zero. The hibernation time counter is a down-counter which does not wrap around after reaching zero value. Interrupt and wakeup events are generated when hibernation timer reaches zero value. When a non-zero value is written into HIBER register hibernation timer is re-started and the respective interrupt is cleared. The relationship between the prescaler and the down counter can be seen in Figure 10-2 below.
XCLK
20-bit Hardware Prescaler
Loadable 8bit Down Counter
1245 HibernationTimer.0
FIGURE
10-2: Hibernation Timer
10.5.1 Hibernation Timer Register (HIBER)
Location Read 7FF3H Write Reset 0 0 0 0 0 0 0 0 7 HIB7 6 HIB6 5 HIB5 4 HIB4 3 HIB3 2 HIB2 1 HIB1 0 HIB0
Symbol HIB[7:0]
Function Hibernation time in 30 second intervals 00H: Hibernation time = 0 seconds 01H: Hibernation time = 30 seconds 02H: Hibernation time = 1 minute 03H: Hibernation time = 1.5 minutes... Continues to increment in 30 second intervals until FFH: Hibernation time = 127.5 minutes
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Advance Information
10.6 Pulse Width Modulators (PWM)
The SST79LF008 device has three independent PWM channels. Each of them has 16-bit prescaler, 8-bit cycle time register, and 8-bit duty cycle control register. The PWM clock can be derived from 8051 core clock CCLK which causes the frequency to be FPWM = FCCLK or from 32.768 KHz crystal oscillator clock XCLK which causes the frequency to be FPWM = 32.768KHz (selected by PWM control register). The prescaler output frequency is determined as FPWMP = FPWM / ((PWMPHn:PWMPLn)+1). The PWM output cycle time can be found as TPWMC = (PWMCn+1) / FPWMP, and the 10.6.1 PWM MMCRs 10.6.1.1 PWM Channel 0 Prescaler Register Low Byte (PWMPL0)
Location Read 7F25H Write Reset 7 PWMPL0 _7 1 6 PWMPL0 _6 1 5 PWMPL0 _5 1 4 PWMPL0 _4 1 3 PWMPL0 _3 1 2 PWMPL0 _2 1 1 PWMPL0 _1 1 0 PWMPL0 _0 1
PWM output Duty Cycle = (PWMDn+1) / (PWMCn+1) x100%. The PWM Duty Cycle specifies the fraction of the PWM cycle for which the output signal is high. In the case where PWMDn = PWMCn the PWM output is always high. If PWMDn > PWMCn, then the PWM output is always low. The device also includes an additional PWM timer with five "555-like" 300ms interval "blinking" outputs for LED control. The clock source for this PWM timer is 32.768 KHz XCLK signal.
10.6.1.2 PWM Channel 1 Prescaler Register Low Byte (PWMPL1)
Location Read 7F26H Write Reset 7 PWMPL1 _7 1 6 PWMPL1 _6 1 5 PWMPL1 _5 1 4 PWMPL1 _4 1 3 PWMPL1 _3 1 2 PWMPL1 _2 1 1 PWMPL1 _1 1 0 PWMPL1 _0 1
10.6.1.3 PWM Channel 2 Prescaler Register Low Byte (PWMPL2)
Location Read 7F29H Write Reset 7 PWMPL2 _7 1 6 PWMPL2 _6 1 5 PWMPL2 _5 1 4 PWMPL2 _4 1 3 PWMPL2 _3 1 2 PWMPL2 _2 1 1 PWMPL2 _1 1 0 PWMPL2 _0 1
Symbol PWMPLn[7:0]
Function PWM channel 0-2 prescaler low byte. When PWMPLn (n=0-2) register is modified, the PWMn output can be unpredictable for no more than one PWMn cycle. The output frequency of the prescaler is FPWM/((PWMPHn:PWMPLn)+1).
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Advance Information 10.6.1.4 PWM Channel 0 Prescaler Register High Byte (PWMPH0)
Location Read 7F97H Write Reset 7 PWMPH0 _7 1 6 PWMPH0 _6 1 5 PWMPH0 _5 1 4 PWMPH0 _4 1 3 PWMPH0 _3 1 2 PWMPH0 _2 1 1 PWMPH0 _1 1 0 PWMPH0 _0 1
10.6.1.5 PWM Channel 1 Prescaler Register High Byte (PWMPH1)
Location Read 7F98H Write Reset 7 PWMPH1 _7 1 6 PWMPH1 _6 1 5 PWMPH1 _5 1 4 PWMPH1 _4 1 3 PWMPH1 _3 1 2 PWMPH1 _2 1 1 PWMPH1 _1 1 0 PWMPH1 _0 1
10.6.1.6 PWM Channel 2 Prescaler Register High Byte (PWMPHn)
Location Read 7F99H Write Reset 7 PWMPH2 _7 1 6 PWMPH2 _6 1 5 PWMPH2 _5 1 4 PWMPH2 _4 1 3 PWMPH2 _3 1 2 PWMPH2 _2 1 1 PWMPH2 _1 1 0 PWMPH2 _0 1
Symbol PWMPHn[7:0]
Function PWM channel 0-2 prescaler high byte. When PWMPHn (n=0-2) register is modified, the PWMn output can be unpredictable for no more than one PWMn cycle. The output frequency of the prescaler is FPWM/((PWMPHn:PWMPLn)+1).
10.6.1.7 PWM Channel 0 Cycle Time Register (PWMC0)
Location Read 7F9AH Write Reset 7 PWMC0 _7 1 6 PWMC0 _6 1 5 PWMC0 _5 1 4 PWMC0 _4 1 3 PWMC0 _3 1 2 PWMC0 _2 1 1 PWMC0 _1 1 0 PWMC0 _0 1
10.6.1.8 PWM Channel 1 Cycle Time Register (PWMC1)
Location Read 7F9BH Write Reset 7 PWMC1 _7 1 6 PWMC1 _6 1 5 PWMC1 _5 1 4 PWMC1 _4 1 3 PWMC1 _3 1 2 PWMC1 _2 1 1 PWMC1 _1 1 0 PWMC1 _0 1
10.6.1.9 PWM Channel 2 Cycle Time Register (PWMC2)
Location Read 7F9CH Write Reset 7 PWMC2 _7 1 6 PWMC2 _6 1 5 PWMC2 _5 1 4 PWMC2 _4 1 3 PWMC2 _3 1 2 PWMC2 _2 1 1 PWMC2 _1 1 0 PWMC2 _0 1
Symbol PWMCn[7:0]
Function PWM channel 0-2 cycle time value. The 8-bit down-counter divides the prescaler output frequency by (PWMCn+1). When PWMCn (n=0-2) register is modified, the PWMn output can be unpredictable for no more than one PWMn cycle.
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Advance Information 10.6.1.10 PWM Channel 0 Duty Cycle Time Register (PWMD0)
Location Read 7F9DH Write Reset 7 PWMD0 _7 1 6 PWMD0 _6 1 5 PWMD0 _5 1 4 PWMD0 _4 1 3 PWMD0 _3 1 2 PWMD0 _2 1 1 PWMD0 _1 1 0 PWMD0 _0 1
10.6.1.11 PWM Channel 1 Duty Cycle Time Register (PWMD1)
Location Read 7F9EH Write Reset 7 PWMD1 _7 1 6 PWMD1 _6 1 5 PWMD1 _5 1 4 PWMD1 _4 1 3 PWMD1 _3 1 2 PWMD1 _2 1 1 PWMD1 _1 1 0 PWMD1 _0 1
10.6.1.12 PWM Channel 2 Duty Cycle Time Register (PWMD2)
Location Read 7F9FH Write Reset 7 PWMD2 _7 1 6 PWMD2 _6 1 5 PWMD2 _5 1 4 PWMD2 _4 1 3 PWMD2 _3 1 2 PWMD2 _2 1 1 PWMD2 _1 1 0 PWMD2 _0 1
Symbol PWMDn[7:0]
Function PWM channel 0-2 duty cycle value. This value defines the number of prescaler clocks for which PWM output is high. When PWMDn (n=0-2) register is modified, the new duty cycle will be in effect starting with the next PWMn cycle. Duty Cycle = ((PWMDn+1) / (PWMCn+1)) x 100% If PWMDn=PWMCn, then PWM output is always high (Duty Cycle = 100%) If PWMDn > PWMCn PWM output is always low (Duty Cycle = 0%)
10.6.1.13 PWM Control Register (PWMCR)
Location Read 7F96H Write Reset 7 PWM4_L ED1 0 6 PWM4_L ED0 0 5 PWM3_L ED1 0 4 PWM3_L ED0 0 3 X 2 PWM2_S EL 0 1 PWM1_S EL 0 0 PWM0_S EL 0
Symbol X PWM[2:0]_SEL
PWM[4:3]_LED[1:0]
Function Not implemented Not defined PWM channel 2-0 clock source Selection bit 1: Select XCLK - FPWM = 32.768KHz, PWM keeps running when 8051 is in Power Down mode. 0: Select 8051 core clock CCLK - FPWM = FCCLK. PWM is stopped when 8051 is in Power Down mode. LED 4-3 output control bits
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Advance Information 10.6.1.14 PWM 555 Like LED Control Register (PWM555CR1)
Location Read 7F21H Write Reset X 0 0 7 6 PWM2_L ED1 5 PWM2_L ED0 4 PWRGOOD PWRGOOD 3 PWM1_L ED1 0 2 PWM1_L ED0 0 1 PWM0_L ED1 0 0 PWM0_L ED0 0
Symbol X PWM[2:0]_LED[1:0] PWRGOOD TABLE 10-6: LED 4/2/0 Behavior
Control Bits: PWM4_LED[1:0] PWM2_LED[1:0] PWM0_LED[1:0] 00 01 10 11
Function Not implemented Not defined LED 2-0 output control bits Status of POWERGOOD Pin (reset value = pass through pin state).
Output Behavior LED4 LED2 LED0 Output high (LED is Off) Output low = 0.125s, Output period = 1.0s Output low =0.125s, Output period = 0.5s Output low (LED is On)
T10-6.1320
TABLE 10-7: LED 3/1 Behavior
Control Bits: PWM3_LED[1:0] PWM1_LED[1:0] 00 01 10 11 Output Behavior LED3 LED1 Output high (LED is Off) Output low = 0.125s, Output period = 3.0s Output low =0.125, Output period = 1.5s Output low (LED is On)
T10-7.1320
Note: 555, like PWM, uses 32.768KHz and runs in Power Down mode.
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Advance Information
11.0 SERIAL I/O PORT (UART) 11.1 Full-Duplex, Enhanced UART
The SST79LF008 serial I/O port is a full-duplex, enhanced UART port that uses the transmit and receiver registers to simultaneously transmit and receive data in the hardware while the software is performing other tasks. The transmit and receive registers are both located in the Serial Data Buffer (SBUF) special function register. Writing to the SBUF register loads the transmit register, while reading from the SBUF register obtains the contents of the receive register. The enhanced UART features framing error detection and automatic address recognition. The UART has four modes of operation which are selected by the Serial Port Mode selection bits (SM0 and SM1) of the Serial Port Control (SCON) special function register. In all four modes, transmission is initiated by any instruction that uses the SBUF register as a destination register. Reception is initiated in mode 0 when the Receive Interrupt (RI) flag bit of the Serial Port Control (SCON) SFR is cleared and the Reception Enable/ Disable (REN) bit of the SCON register is set. Reception is initiated in the other modes by the incoming start bit, if the REN bit of the SCON register is set.
11.2 Framing Error Detection
Framing Error Detection allows checking for valid stop bit during receive operation in serial modes 1, 2, and 3. An incorrect stop bit could be caused by noise in the serial line, simultaneous transmissions by two CPUs, or mismatched baud rates between transmitter and receiver. Serial mode 0 does not permit Framing Error Detection because it employs a synchronous serial protocol that does not use stop bit. Framing Error Detection is selected in the PCON register by setting SMOD0 = 1, see Figure 11-1. If a stop bit is missing, the Framing Error bit (FE) at SCON[7] will be set. The software examines the FE bit after each received bit to check for data errors. After the FE bit is set, it can only be cleared by software. Valid stop bits do not clear the FE bit. When Framing Error Detection is enabled, RI rises on the stop bit, instead of the last data bit. See Figures 11-2 and 11-3.
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
SCON
(98H)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD0 = 0) SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL
PCON
(87H)
To UART framing error control
1245 FramErrBlkDiag.0
FIGURE
11-1: Framing Error Block Diagram
RXD
D0 Start bit
D1
D2
D3
D4
D5
D6
D7 Stop bit
Data byte
RI SMOD0=X FE SMOD0=1
1245 UART Mode1.0
FIGURE
11-2: UART Timings in Mode 1
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Advance Information
RXD
D0 Start bit
D1
D2
D3
D4
D5
D6
D7
D8 Ninth bit Stop bit
Data byte
RI SMOD0=0 RI SMOD0=1 FE SMOD0=1
1245 UART MOde2-3.0
FIGURE
11-3: UART Timings in Modes 2 and 3 by a valid stop bit. Note that AAR is not available in mode 0. Setting SM2 bit in the SCON register in mode 0 will have no effect. 11.3.1 Using the Given Address to Select Slaves Given addresses are used to address an individual slave or a group of slaves. A slave may have one or more given addresses because of "don't care" bits. The given address is computed by a logical AND operation of the SADDR value and the SADEN value. Any bit masked off by a 0 from SADEN becomes a "don't care" represented by `X' in the example below.
Slave 1 SADDR SADEN GIVEN
11.3 Automatic Address Recognition
Automatic Address Recognition helps reduce the time and power required to interface and communicate with multiple serial devices. All connected devices share the same serial link, and each device has its own address. In this configuration, a device is only interrupted when it receives its own address, group address, or broadcast address. This process eliminates the software overhead to compare addresses. Automatic Address Recognition saves power by working in conjunction with the idle mode, thereby reducing the system's overall power consumption. Since there may be multiple slaves connected serially to one master, only one slave would have to be interrupted from the idle mode to respond to the master's transmission. During this transmission, Automatic Address Recognition (AAR) allows all the other slaves to remain in idle mode. Limiting the number of interruptions reduces the total current drawn from the system. There are two ways to communicate with slaves--by group or all at once. To communicate with a group of slaves, the master sends out an address called the "given address". To communicate with all the slaves, the master sends out an address called the "broadcast" address. Enable AAR in mode 2 or 3 (9-bit modes) by setting the SM2 bit in SCON. Each slave has its own SM2 bit set waiting for an address byte (9th bit = 1). The Receive Interrupt (RI) flag will only be set when the received byte matches either the given address or the broadcast address. Next, the slave then clears its SM2 bit to enable reception of the data bytes (9th bit = 0) from the master. When the 9th bit = 1, the master is sending an address. When the 9th bit = 0, the master is sending the actual data. If mode 1 is used, the stop bit takes the place of the 9th bit. Bit RI is set only when the received command frame address matches the device's address, and is terminated
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= = =
1111 1111 1111
0001 1010 0X0X
Slave 2 SADDR SADEN GIVEN
= = =
1111 1111 1111
0011 1001 0XX1
Because of the "don't care" bits, multiple slaves may respond to a given address as shown in Table 11-1. Continuing the above example, slave 1 has an individual address of 11110001 loaded into SADDR. The SADEN byte has been used to mask off bits for a given address to allow more combinations of selecting slave 1 and 2. In this case for the given addresses, the last bit (LSB) of slave 1 is a "don't care" and the last bit slave 2 is a 1. Similarly for slave 2, the second to last bit is a "don't care" and that of slave 1 is a 0. Thus to communicate with slave 1 and 2, the master would need to send an address with the last two bits equal to 01 (e.g. 1111 0001). To communicate with slave 1 only, the last two bits must be 00 (e.g. 1111 0000).
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Advance Information TABLE 11-1: Possible Addresses for Slaves 1 and 2
Target Slave Slave 1 only Slave 2 only Slave 1 and 2 Given Address 1111 0X0X 1111 0XX1 1111 0XXX All Possible Addresses 1111 0000 1111 0100 1111 0111 1111 0011 1111 0001 1111 0101
T11-1.0 1320
If the user added a third slave, the slave 3 example in Table 11-2 provides its Given Address calculation, and Table 112 indicates all possible addresses for Slave 3 and the combination of Slaves 2 and 3.
Slave 3 SADDR SADEN GIVEN
= = =
1111 1111 1111
1001 0101 X0X1
TABLE 11-2: Possible Addresses for Slave 3 and Slave 2/3 Combination
Target Slave Slave 3 only Slave 2 and 3 only Given Address 1111 X0X1 1111 XXX1 All Possible Addresses 1111 1011 1111 1001 1111 0011
T11-2.0 1320
11.3.2 Using the Broadcast Address to Select Slaves Using the Broadcast Address, the master can communicate with all the slaves at once. The broadcast address is formed by performing a logical OR of SADDR and SADEN with zeros in the result treated as "don't cares".
Slave 1 1111 0001 + 1111 1010 1111 1X11 = SADDR = SADEN = Broadcast
"Don't cares" allow for a wider range in defining the Broadcast Address, but in most cases, the Broadcast Address will be FFH. On reset, SADDR and SADEN are `0'. This produces a Given Address of all "don't cares" as well as a Broadcast Address of all "don't cares". This effectively disables Automatic Addressing mode.
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Advance Information
11.4 UART SFRs
11.4.1 Power Control Register (PCON)
Location Read 87H Write Reset 0 0 0 1 0 0 0 0 7 SMOD1 6 SMOD0 5 BOF1 4 POF1 3 GF1 2 GF0 1 PD 0 IDL
1. These bits are reset by Power-On reset only (all other reset events have no affect)
Symbol SMOD1 SMOD0
BOF
POF GF1 GF0 PD
IDL
Function Double baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate, and the serial port is used in modes 1, 2, and 3, then baud rate is doubled. FE bit / SM0 bit selection control bit. 1: SCON[7] = FE bit 0: SCON[7] = SM0 bit Brown-out detection status flag. Set when brown-out is detected, cleared by software. This bit is also cleared after Power-On reset. It is not affected by any other reset event. Power-on reset status flag. Set after POR, cleared by software. This bit is not affected by any other reset event. General-purpose flag bit General-purpose flag bit Power Down mode bit. Setting this bit activates Power Down mode (refer to Figure 5-3). It is cleared by hardware after exiting Power Down mode by one of the reset (see Table 5-1) or enabled wakeup event (see Figure 8-1 through Figure 8-5). 1: Activates Power Down mode 0: Power Down mode is not activated Idle mode bit. Setting this bit activates Idle mode (refer to Table 5-3). It is cleared by hardware after exiting from Idle mode by one of the reset (see Table 5-1) or enabled interrupt event, see Figure 8-1 through Figure 8-5. 1: Activates idle mode 0: Idle mode is not activated
11.4.2 Slave Address Register (SADDR)
Location Read A9H Write Reset 0 0 0 0 0 0 0 0 7 SADDR7 6 SADDR6 5 SADDR5 4 SADDR4 3 SADDR3 2 SADDR2 1 SADDR1 0 SADDR0
Symbol SADDR[7:0]
Function UART slave address
11.4.3 Slave Address Mask Register (SADEN)
Location Read B9H Write Reset 0 0 0 0 0 0 0 0 7 SADEN7 6 SADEN6 5 SADEN5 4 SADEN4 3 SADEN3 2 SADEN2 1 SADEN1 0 SADEN0
Symbol SDAEN[7:0]
Function UART slave address mask
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Advance Information 11.4.4 Serial Port UART Data Register (SBUF)
Location Read 99H Write Reset X X X X X X X X 7 SBUF7 6 SBUF6 5 SBUF5 4 SBUF4 3 SBUF3 2 SBUF2 1 SBUF1 0 SBUF0
Symbol X SBUF[7:0]
Function Not defined UART data buffer
11.4.5 Serial Port Control Register (SCON)
Location Read 98H Write Reset 0 0 0 0 0 0 0 0 7 SM0/FE 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Symbol FE
SM0 SM1 SM2
REN
TB8 RB8 TI
RI
Function Framing Error bit (set SMOD0 = 1 to access FE bit) 1: Framing Error. Set by receiver when invalid stop bit is detected, cleared by software 0: No framing error detected Serial Port Mode Bit 0 (clear SMOD0 = 0 to access SM0 bit) Serial Port Mode Bit 1 Enables the Automatic Address Recognition feature in Modes 2 or 3. In these modes, if SM2 = 1 then RI will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast address. In Mode 1, if SM2 = 1 then RI will not be set unless a valid stop bit has been received. In Mode 0, SM2 should be 0. Enables serial reception 1: Enable reception. 0: Disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. This bit is set or cleared by software as desired. In Modes 2 and 3, RB8 is the 9th data bit that has been received. In Mode 1, if SM2 = 0, RB8 is the stop bit that has been received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
TABLE 11-3: Serial Port Mode Description
SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description Shift Register 8-bit UART 9-bit UART 9-bit UART Baud Rate1 FCCLK / 12 Variable2,3 FCCLK /16 (SMOD1 =1) or FCCLK /32 (SMOD1 = 0) Variable2,3
T11-3.0 1320
1. FCCLK = 8051 core clock frequency 2. Variable baud rate if T1 is used as rate generator = (2SMOD1)*(T1 overflow rate)/32 3. Variable baud rate if T2 is used as rate generator = (T2 overflow rate)/16
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Advance Information
12.0 SERIAL PERIPHERAL INTERFACE (SPI) 12.1 SPI Features
* * * * * * * * * Master or slave operation 16 MHz bit frequency (max) master mode 8 MHz bit frequency (max) slave mode LSB first or MSB first data transfer Four programmable bit rates End of transmission interrupt (SPIF) Write collision flag protection (WCOL) Wake up from Idle (master and slave modes) Wake up from Power Down modes (slave mode only) then shifted out of the MOSI (GPIO3) pin into the MOSI pin of the slave device. Following a complete transmission of one byte of data, the SPI clock generator is stopped and the SPIF flag is set. An SPI interrupt request will be generated if the SPI Interrupt Enable bit (SPIE) is set. When SST79LF008 slave mode is selected, an external master generates SCK clock and drives the Slave Select input pin SS# (GPIO6) low to select the SST79LF008 SPI module as a slave. If the Slave Select input pin has not been driven low, then the SST79LF008 SPI unit is not active and the MOSI port can also be used as an input port pin. Clock Phase control bit (CPHA) and Clock Polarity (CPOL) control the phase and polarity of the SPI clock. Figures 12-2 and 12-3 show the transfer formats with four possible combinations of these two bits. To wake up the SST79LF008 from IDLE, whether in master or slave mode, the following conditions must be met: The SPIF bit is set to `1' upon completion of the data transfer, the SPIE is `1', and EA (Enable Global Interrupt bit in interrupt enable register) is `1'. These conditions generate an interrupt that wakes the device from IDLE mode. In slave mode only, the SST79LF008 wakes up from Power Down when CPHA = 0 or CPHA = 1. When CPHA = 0, a transition from high to low on SS# pin wakes up the device from Power Down mode. When CPHA = 1, the clock edges of SCK wakes up the device from Power Down mode.
12.2 SPI Description
The serial peripheral interface (SPI) allows full-duplex highspeed synchronous data transfer between the SST79LF008 and the peripheral devices. Figure 12-1 shows the correspondence between master and slave SPI devices. The SCK (GPIO5) pin is the clock output for master mode and input for slave mode. The SST79LF008 does not output SS#. If the SST79LF008 is the master and there is only one slave device, the slave's SS# input can be tied low. If there is more than one slave, N GPIOs can be used to select N slaves. Another option is external generation of the SS# inputs of multiple slave devices. When SST79LF008 master mode is selected, the SPI clock generator will start following a write to the SST79LF008 device SPI data register. The written data is
MSB Master LSB MISO 8-bit Shift Register MISO
MSB Slave LSB 8-bit Shift Register
MOSI
MOSI
SPI Clock Generator
SCK
SCK SS#
MISO = Master In Slave Out MOSI = Master Out Slave In
VIL
1245 SPIMasterSlave.0
FIGURE
12-1: SPI Master-Slave Interconnection
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Advance Information
12.3 SPI Transfer Formats
SCK Cycle # (for reference) SS# (to Slave) SCK (CPOL=0) SCK (CPOL=1) MOSI (to Slave) MISO (from Slave) MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
1245 XferCPHA.0.1
1
2
3
4
5
6
7
8
FIGURE
12-2: SPI Transfer Format (CPHA = 0)
SCK Cycle # (for reference) SS# (to Slave) SCK (CPOL=0) SCK (CPOL=1) MOSI (to Slave) MISO (from Slave)
1
2
3
4
5
6
7
8
MSB MSB
6 6
5 5
4 4
3 3
2 2
1 1
LSB LSB
1245 XferCPHA_1.1
FIGURE
12-3: SPI Transfer Format (CPHA = 1)
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Advance Information
12.4 SPI SFRs
12.4.1 SPI Control Register (SPCR)
Location Read D5H Write Reset 0 7 SPIE 6 X 5 DORD 0 4 MSTR 0 3 CPOL 0 2 CPHA 1 1 SPR1 0 0 SPR0 0
Symbol X SPIE
DORD
MSTR
CPOL
CPHA
SPR1, SPR0
Function Not implemented Not defined SPI end of transmission Interrupt Enable bit 1: Enable SPI interrupt 0: Disable SPI interrupt Data Transmission Order 1: LSB first in data transmission 0: MSB first in data transmission Master/Slave select 1: Select Master mode 0: Select Slave mode Clock Polarity 1: SCK is high when idle (Active Low) 0: SCK is low when idle (Active High) Clock Phase control bit 1: Shift-in triggered on the trailing edge of the clock 0: Shift-in triggered on the leading edge of the clock SPI Clock Rate Select bits These two bits together with SPR2 bit in CLKCON register control the SCK rate of the device configured as a master. SPR2 bit has no effect on the slave. The relationship between SCK and 8051 core clock frequency, FCCLK, as shown in Tables 12-1 and 12-2.
TABLE 12-1: SCK Rate as a Function of SPI Clock Rate Select Bits (Master Only)
SPR2 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 SCK Frequency = FCCLK divided by 4 16 64 128 2 8 32 64
T12-1.1320
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Advance Information TABLE 12-2: SCK Rate as a Function of SPI Clock Rate Select Bits (Slave Only)
SPR1 0 0 1 1 SPR0 0 1 0 1 SCK Frequency = FCCLK divided by 4 16 64 128
T12-2.
12.4.2 SPI Status Register (SPSR)
Location Read AAH Write Reset 0 0 X X X X X X 7 SPIF 6 WCOL 5 4 3 2 1 0 -
Symbol X SPIF
WCOL
Function Not implemented Not defined SPI Interrupt Flag. Set upon completion of data transfer. If SPIE = 1, an interrupt is then generated. Cleared by software. This bit is also automatically cleared by any access to SPDR after reading SPSR with SPIF=1. Write Collision Flag. Set if SPI data register is written during data transfer. Cleared by software. This bit is also automatically cleared by any access to SPDR after reading SPSR with WCOL=1.
12.4.3 SPI Data Register (SPDR)
Location Read 86H Write Reset 0 0 0 0 0 0 0 0 7 SPDR7 6 SPDR6 5 SPDR5 4 SPDR4 3 SPDR3 2 SPDR2 1 SPDR1 0 SPDR0
Symbol SPD[7:0]
Function SPI data. When read, returns received data. When written to, the data is to be transmitted. Writing to this register during transfer will be ignored, and will set WCOL bit.
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Advance Information
13.0 SMBUS INTERFACE 13.1 SMBus Features
* * * * * * * * Compatible with SMBus 2.0 specification Two SMBus controllers and three SMBus channels Selection of SMBus channels through the internal multiplexer Support for SMbus master and slave operation Software-defined slave address and General Call address support Support for both polling and interrupt driven operation Wake up from Idle and Power Down--slave mode Wake up from Idle--master mode
13.2 SMBus Channels
The SST79LF008 includes two SMBus controllers, which support three separate two-wire SMBus channels. Each channel consists of Serial Data Line (SDAn, n=0-2) and the Serial Clock Line (SCLn, n=0-2). SMBus controller 0 controls the clock and data lines of the SMBus channel 0 (SCL0,SDA0), SMBus controller 1 controls via internal multiplexer the clock and data lines of SMBus channel 1 (SCL1, SDA1) and SMBus channel 2 (SCL2, SDA2). See Figure 13-1. SSCR, in Register 13.7.1, contains SM1_EN, SM0_EN, and CHSEL1
Clock SMBus Controller0 Data SM1_EN SM0_EN Clock SMBus Controller1 Data
SCL0 SDA0
SCL1 SDA1 SCL2 SDA2
CHSEL1
Multiplexer
SST79LF008
1245 SMBus_BlockDia.0
FIGURE
13-1: SMBus Module Block Diagram
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Advance Information
13.3 SMBus Protocol Overview
SMBus is a bidirectional two-wire bus, which allows multiple master and slave devices to be connected simultaneously. All SMBus devices must have open drain outputs. The SMBus lines are connected externally to a positive voltage source (up to 5V) via pull-up circuits, and remain high when they are not driven by SMBus devices. The bus master device initiates the SMBus protocol, controls the bus clock, and terminates the transaction. The slave device responds and transmits the requested data back to the bus master device. Both master and slave devices on the bus can either operate as a transmitter or as a receiver. Figures 13-2 and 13-3 illustrate bit and byte transfer layers of SMBus interface.
SDAn SCLn Data Line Stable Change of Data Valid Data Allowed
1245 SMBus_Bit_Xfer.0
FIGURE
13-2: SMBus Relationship of SDAn to SCLn for Bit Transfer
ACK from receiver SDAn MSB S SCLn Start ACK Byte Transfer Complete Receiver holds clock line low while byte is processed
1245 SMBus_Data_Xfer
1
2
3-6
7
8
9
1
2
3-8
9 ACK
P Stop
FIGURE
13-3: SMBus Byte Transfer At each clock cycle, the slave can hold SCLn low for an extended period of time when the slave is still handling the previous data or is preparing a new data. There are typically two cases which may cause the slave to hold the bus: a byte received has not been processed, or the next byte to be transmitted is not ready. Under these circumstances, the slave will extend the clock low state. The SMBus bytes are always transferred with the most significant bit first. An acknowledgement (ACK) cycle is appended at the end of each data byte (i.e., each byte transfer requires nine clock pulses with ACK being the ninth clock). The clock pulse for SMBus ACK clock cycle is always generated by the master device, but the ACK data bit is sent by the receiving device (master or slave). The transmitter must release the data line SDAn during ACK clock allowing the receiver to control the data line. The receiver asserts a low level on the data line during the ACK clock pulse to acknowledge that it has received the last data byte correctly.
As shown on Figure 13-3, each SMBus transfer is initiated by the master with SMBus start condition (S), and terminated with the stop condition (P). The START condition is created by a high to low transition of the data line SDAn while the clock line SCLn is high. The STOP condition is created by a low to high transition of the data line SDAn while the clock line SCLn is high. The bus is considered to be "busy" after a START condition. The bus status will remain "busy" until a STOP condition is detected. Between START and STOP condition, the SMBus protocol permits all information including address, command, and data to be transmitted on a serial data line, SDAn, synchronized with a serial clock SCLn. A single data bit is transferred per each SCLn clock pulse. As shown on Figure 132, throughout the SCLn clock's high period, the data on SDAn line is kept stable by the transmitter, and can be sampled by the receiver. New data is sent by the transmitter only during the low state of the SCLn clock.
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Advance Information If invalid command or data is detected or the receiver is busy, it may send a negative acknowledge (NACK) to indicate that it will not accept any additional data bytes. NACK is recognized when a high level is detected on the data line during the ACK clock pulse. There is an exception when NACK must be generated after a valid byte transfer. If the bus master is the receiver, it must indicate to the slave transmitter an end of data. It does this by responding with NACK to the last byte clocked out of the slave device. Each slave device on the SMBus must have a unique slave address. The master transmits the address of the targeted slave device in the first seven bits after a START condition. The eighth bit, R/W#, specifies the direction of data transfer. See Figure 13-4. The slave device can operate as a transmitter or a receiver depending on the value of R/W# bit (1= slave transmitter, 0=slave receiver). The slave device must always acknowledge its own address.
SDAn S SCLn Start Address R/W ACK Data ACK Data ACK Stop
1245 SMBus_Addr_Xfer
1-7
8
9
1-7
8
9
1-7
8
9
P
FIGURE
13-4: SMBus Address Transfer lost. In this case, the losing master must immediately switch to the slave receiver mode, and acknowledge its own slave address. See System Management Bus specification, Version 2.0 for more details on SMBus protocol.
It is possible for multiple masters to generate a START condition and then continue the transfer simultaneously. An arbitration mechanism is provided by the SMBus protocol for this case. Arbitration takes place on the SDAn line to prevent contention on the bus between masters while the SCLn line is at the high level. If a master attempts to send data bit `1' over the bus, and detects SDAn at a low level driven by another master, it will abort the data transfer because the current level on the bus does not match its own. The master that loses the arbitration can generate clock pulses until the end of the last-transmitted data byte. If a master loses the arbitration during the addressing phase, it is possible that the master which has won the arbitration was attempting to address the master which has
13.4 SMBus MMCRs
There are four MMC registers associated with each of the two SMBus controllers. These registers are Multi-master bus control register, Multi-master bus control/status register, Multi-master bus address register, and Multi-master bus transmit/receive data shift register. In addition there are two registers common for both controllers: SMBus switch register and SMBus line status register. All register types are explained in Table 13-1.
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Advance Information TABLE 13-1: SMBus MMCRs
Bit Address, Symbol, or Alternative Port Function Symbol SMCR0 Description Multi-Master Bus Control Multi-Master Bus Control / Status Multi-Master Bus Address Multi-Master Bus Transmit / Receive Data Shift Multi-Master Bus Control Multi-Master Bus Control / Status Register Multi-Master Bus Address Multi-Master Bus Transmit / Receive Data Shift SMBus Line Status Register SMBus Switch Control Register Address 7F31H MSB
ACKEN CLKSEL INTEN INT TXCLK3 TXCLK2 TXCLK1
Reset Value LSB
TXCLK0
00H
SMSR0
7F32H
SMSR0_ SMSR0_ SMSR0_ SMSR0_ SMSR0_ MOD1 MOD0 BSY SEREN ARB SAR0[7:0] SDSR0[7:0]
SMSR0_ ADDRS
SMSR0_ ADDR0
SMSR0_ ACK
00H
SAR0 SDSR0
7F33H 7F34H
0000000xb 00H
SMCR1
7F67H
ACKEN
CLKSEL
INTEN
INT
TXCLK3
TXCLK2
TXCLK1
TXCLK0
00H
SMSR1
7F68H
SMSR1_ SMSR1_ SMSR1_ SMSR1_ SMSR1_ MOD1 MOD0 BSY SEREN ARB
SMSR1_ ADDRS
SMSR1_ ADDR0
SMSR1_ ACK
00H
SAR1 SDSR1
7F69H 7F6AH
SAR1[7:0] SDSR1[7:0]
0000000xb 00H
SLSR1
7F88H
-
-
SCL2
SDA2
SCL1
SDA1
SCL0
SDA0
-
SSCR
7F89H
SM1_EN SM0_EN
-
-
-
P1_SEL
UART_ SM
CHSEL1
00xxx001b
T13-1.1245
1. No reset value is specified for SLSR since this is just pass through register.
13.5 SMBus Multi-master Control and Status Registers
The SMBus control and status registers are used to control SMBus operations. 13.5.1 Multi-Master Bus Control Register (SMCR0)
Location Read 7F31H Write Reset 7 SMCR0_ ACKEN 0 6 SMCR0_ CLKSEL 0 5 SMCR0_ INTEN 0 4 SMCR0_ INT 0 3 SMCR0_ TXCLK3 0 2 SMCR0_ TXCLK2 0 1 SMCR0_ TXCLK1 0 0 SMCR0_ TXCLK0 0
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Advance Information 13.5.2 Multi-Master Bus Control Register (SMCR1)
Location Read 7F67H Write Reset 7 SMCR1_ ACKEN 0 6 SMCR1_ CLKSEL 0 5 SMCR1_I NTEN 0 4 SMCR1_I NT 0 3 SMCR1_ TXCLK3 0 2 SMCR1_ TXCLK2 0 1 SMCR1_ TXCLK1 0 0 SMCR1_TX CLK0 0
Symbol SMCRn_ACKEN
SMCRn_CLKSEL
SMCRn_INTEN
SMCRn_INT
SMCRn_TXCLK[3:0]
Function Acknowledge enable bit (for SST79LF008 operation as a receiver) (n = 0-1) 1: Enable ACK generation (SDAn is driven low during ACK cycle) 0: Disable ACK generation (SDAn is not driven = SDAn "floats" during ACK cycle) SCL clock prescaler control (n = 0-1) 1: FPSCL = FCCLK/256 0: FPSCL = FCCLK /16 FCCLK = 8051 core clock frequency SMBus controller Interrupt Enable bit (must be always set for normal operation-- use INTSRCAMSK register bits to mask SMBus interrupts if necessary) (n = 0-1) 1: Enabled Interrupt 0: Disabled Interrupt SMBus interrupt pending flag. This bit is set by hardware, and cleared when software is writing `0'. Writing `1' to this bit will be ignored. (n = 0-1) 1: Interrupt is pending (SMBus is stalled as SCLn line is held low) 0: No interrupt pending Events that set SMCR1_INT in hardware include: When an 1-byte transmission or receiving operation is completed When a general call or a slave address match occurs When bus arbitration fails SMBus clock selection control (for SST79LF008 operation as a master) (n = 0-1) SMBus clock frequency = FPSCL /(SMCR1_TXCLK[3:0] + 1). Must not be set 000x if SMCR1_CLKSEL = 0.
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Advance Information 13.5.3 Multi-Master Bus Control / Status Register 0 (SMSR0)
Location Read 7F32H Write Reset 0 0 0 0 7 SMSR0 _MOD1 6 SMSR0 _MOD0 5 SMSR0 _BSY 4 SMSR0 _SEREN 3 SMSR0 _ARB 0 2 SMSR0 _ADDRS 0 1 SMSR0 _ADDR0 0 0 SMSR0 _ACK 0
Symbol -
Function Not implemented
13.5.4 Multi-Master Bus Control / Status Register 1 (SMSR1)
Location Read 7F68H Write Reset 0 0 0 0 7 SMSR1 _MOD1 6 SMSR1 _MOD0 5 SMSR1 _BSY 4 SMSR1 _SEREN 3 SMSR1 _ARB 0 2 SMSR1 _ADDRS 0 1 SMSR1 _ADDR0 0 0 SMSR1 _ACK 0
Symbol SMSRn_MOD[1:0]
SMSRn_BSY
Function Not implemented SMBus controller mode selection bits (n = 0-1) SMBus controller mode. Selection as a function of SMSRn_MOD bits. 00 Slave receive mode 01 Slave transmit mode 10 Master receive mode 11 Master transmit mode Normally these bits should be modified by software only when SMBus is idle. If they are modified during data transfer, unexpected results could occur. One exception is when MODE[1:0] is changed in order to generate a REPEATED START condition after the last byte of the current transaction is received or transmitted. Both SMSRn_MOD0 and SMSRn_MOD1 bits are cleared by hardware automatically when: 1) SMBus STOP condition is detected 2) When SEREN bit is cleared 3) SMBus arbitration failure is detected SMSRn_MOD0 bit is also set/cleared by hardware equal to the value of R/W# bit of the address phase, when SMBus controller is in slave mode. (n = 0-1) When read, this bit indicates the bus busy status (SMBus is busy between START and STOP conditions). When written to, this bit controls generation of START and STOP conditions for SMBus controller in master mode. 1: When read: the bus is busy When written: START condition is generated, regardless of current SMBus busy status 0: When read: the bus is not busy When written, STOP condition is generated only if SMBus was already busy. To generate START condition when bus is idle (BSY='0'), software should write `1' to SEREN, SMSRn_MOD1, and BSY bits simultaneously. To generate a REPEATED START current when bus is already busy (BSY='1'), software should write `1' to SMSRn_MOD1, BSY, and SEREN bits simultaneously, and then clear INT bit to release the bus. To generate a STOP condition when bus is already busy (BSY='1') software should write `1' to bits SEREN and SMSRn_MOD1 while writing `0' to BSY bit simultaneously, and then clear INT bit to release the bus. (n = 0-1)
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Advance Information SMSRn_SEREN SMBus Serial output Enable bit 1: Enable SMBus Receive/Transmit over SDAn and SCLn 0: Disable SMBus Receive/Transmit: MOD[1:0] are cleared, SDAn, SCLn are floated The order of floating SDAn and SCLn is as follows: SCLn floats first, then SDAn floats. Therefore, disabling serial outputs when SST79LF008 is a transmitter may create a STOP condition on the bus if the last transmitted data bit was `0'. (n = 0-1) Arbitration status flag 1: Bus arbitration failed 0: No bus arbitration failure detected This bit is automatically cleared when START/STOP condition is detected. (n = 0-1) Slave Address match status 1: Received slave address matches the address value in SAR 0: No slave address match detected Both ARB and ADDRS bits will be set if arbitration failed during address phase, and address sent by the other master matches SAR setting.This bit is automatically cleared when START/STOP condition is detected. (n = 0-1) Broadcast Address match status flag 1: Received slave address is the broadcast address 00H 0: No broadcast address match is detected Both ARB and ADDRS bits will be set if arbitration failed during address phase, and address sent by the other master is the broadcast address.This bit is automatically cleared when START/STOP condition is detected. (n = 0-1) Last-received bit status flag (n = 0-1) 1: Last-received bit is `1' (ACK was not received) 0: Last-received bit is `0' (ACK was received)
SMSRn_ARB
SMSRn_ADDRS
SMSRn_ADDR0
SMSRn_ACK
13.6 Multi-master Bus Address and Data Shift Registers
The SMBus address register is used to store the slave address of the respective SMBus controller. 13.6.1 Multi-Master Bus Address Register 0 (SAR0)
Location Read 7F33H Write Reset 0 0 0 0 0 0 0 X 7 SAR0_7 6 SAR0_6 5 SAR0_5 4 SAR0_4 3 SAR0_3 2 SAR0_2 1 SAR0_1 0 -
13.6.2 Multi-Master Bus Address Register 1 (SAR1)
Location Read 7F69H Write Reset 0 0 0 0 0 0 0 X 7 SAR1_7 6 SAR1_6 5 SAR1_5 4 SAR1_4 3 SAR1_3 2 SAR1_2 1 SAR1_1 0 -
Symbol X SARn[7:1]
Function Not Implemented Not defined These bits holds the 7-bit slave address of the respective SMBus controller in the slave mode, they are compared with the data received from the master in the address phase. When address match is detected slave address match ADDRS bit, and SMBus pending interrupt INT bit will be both set. This register can only be written when SEREN = 0. When SAR is read, it always return previously written data. (n = 0-1)
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Advance Information The SMBus transmit/receive data register acts as a serial shift register and read buffer for interfacing with the SMBus. This register performs all read and write operation from/to the SMBus. In the receiver mode, the SMBus data is shifted into the data register until the acknowledge phase. Further reception of data is inhibited (SCL held low) until the interrupt pending bit INT is cleared. In the transmitter mode, if the SEREN bit is set, the data is transmitted to the SMBus as soon as it is written to the data register. Further transmission of data is inhibited (SCL held low) until the interrupt pending bit INT is cleared.
13.6.3 Multi-Master Bus Transmit / Receive Data Shift Register 0 (SDSR0)
Location Read 7F34H Write Reset 0 0 0 0 0 0 0 0 7 SDSR0_7 6 SDSR0_6 5 SDSR0_5 4 SDSR0_4 3 SDSR0_3 2 SDSR0_2 1 SDSR0_1 0 SDSR0_0
13.6.4 Multi-Master Bus Transmit / Receive Data Shift Register 1 (SDSR1)
Location Read 7F6AH Write Reset 0 0 0 0 0 0 0 0 7 SDSR1_7 6 SDSR1_6 5 SDSR1_5 4 SDSR1_4 3 SDSR1_3 2 SDSR1_2 1 SDSR1_1 0 SDSR1_0
Symbol SDSRn[7:0]
Function Data shift register (n = 0-1) When written to, transmit data to the SMBus provided SEREN = 1 (write is ignored if SEREN = 0). When read, returns the latched value received from SMBus during the last read operation. In address phase of master mode for SMBus controller 0 (controller 1) bit SDSR0 in SDSR0 (SDSR1) register is equal to the inverse of SMSRn_MOD0 bit in the respective SMSR0 (SMSR1) register. In other words, if it is master transmit mode, then SDSR0 equals to `0'; if it is master receive mode, then SDSR0 equals to `1'.
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Advance Information
13.7 SMBus Switch Control and Line Status Registers
The SMBus Switch Control register is used to enable/disable both SMBus controllers, as well as to control the SMBus multiplexer, as shown on Figure 13-1. The SMBus Line status register is used to monitor the SMBus line status. 13.7.1 SMBus Switch Control Register (SSCR)
Location Read 7F89H Write Reset 0 0 X X X 0 7 SM1_EN 6 SM0_EN 5 4 3 2 P1_SEL 1 UART_S M 0 0 CHSEL1 1
Symbol X SM1_EN SM0_EN P1_SEL UART_SM CHSEL1
Function Not Implemented Not defined SMBus controller 1 Enable bit 1: SMBus controller 1 is enabled 0: SMBus controller 1 is disabled and reset to the default state SMBus controller 0 Enable bit 1: SMBus controller 0 is enabled 0: SMBus controller 0 is disabled and reset to the default state Port1/GPIO86-GPIO93 Selection bit 1: Select 8051 Port1 function 0: Select normal GPIO86-GPIO93 function UART and SMBus Channel 1 Selection bit 1: UART RXD/TXD function is selected as alternate function for GPIO53/GPIO54 0: SDA1/SCL1 function is selected as alternate function for GPIO53/GPIO54 Channel Selection for SMBus controller 1 1: Select SMBus channel 1. SCL1 and SDA1 pins are driven by the SMBus controller 1, SCL2 and SDA2 pins are tri-stated 0: Select SMBus channel 2. SCL2 and SDA2 pins are driven by the SMBus controller 1. SCL1 and SDA1 pins are tri-stated.
13.7.2 SMBus Line Status Register (SLSR)
Location Read 7F88H Write Reset X X 7 6 5 SCL2 SCL2 4 SDA2 SDA2 3 SCL1 SCL1 2 SDA1 SDA1 1 SCL0 SCL0 0 SDA0 SDA0
Symbol X
Function Not implemented Not defined
13.8 SMBus Operations
After the SST79LF008 chip resets, both SMBus controllers are disabled. The 8051 firmware can enable each controller and configure SMBus channels via SSCR, GPIODSEL, and GPIOGSEL registers. The firmware can also specify the SMBus clock frequency and enable SMBus interrupts 13.8.1 Master Transmit Mode In Master Transmit Mode, the master addresses the slave by sending the slave address, then the master will transmit data to the slave, and terminates the transfer after all data has been transmitted. in SMCR0 or SMCR1 registers, and load slave addresses to the respective SAR0 or SAR1 registers. Then SST79LF008 is ready for SMBus transmit/receive transactions--a typical example is described in Figure 13-5.
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Advance Information
Set SMSR - Write D0H to SMSR (This is done by software)
a) Write Slave Address to SDSR b) Set BSY bit in SMSR (=F0H) (This is done by software)
Generate START Condition (This is done by hardware)
Send SDSR data byte, Receive ACK bit. Set INT bit in SMCR (This is done by hardware)
More Data to Transmit? (Done by software) YES Write New Data to Transmit to SDSR (This done by software)
NO
a) Clear BSY bit in SMSR (=D0H) b) Clear INT bit in SMCR (This is done by software)
Generate STOP Condition (This done by hardware)
Clear INT bit in SMCR (This done by software)
END
1245 SMBus_Master_XmitMode.0
FIGURE
13-5: SMBus Master Transmit Mode Operation Note that in the case of successful transmission, allowing that arbitration has not failed, the slave is expected to send back an ACK to the master-- lowering the SDAn line during ACK clock. 4. Check for more data to transfer. If the master has more data to transfer, the software will write the next data byte to SDSR and clear the interrupt pending bit in SMCR. This causes the data in SDSR to be sent automatically over the SMBus by controller hardware and returns to Step 3. If the master has no data to transfer, the software will clear the BSY bit in SMSR and clear the interrupt pending bit in SMCR. The controller hardware will generate a STOP condition and release the SMBus lines which completes the transaction.
Figure 13-5 illustrates interaction between 8051 firmware and SMBus controller hardware in Master Transmit mode: Master Transmit Mode 1. Write D0H to SMSR. This presets the SMBus controller for Master Transmit mode. 2. Write a 7-bit slave address to SDSR[7-1], and `0' to SDSR[0] (R/W# bit). The R/W# bit determines the direction of the transfer--if R/W# = 0 then the master will send data to the slave. Set the BSY bit in SMSR register. SMBus controller will generate a START condition and automatically send SDSR data over the SMBus. 3. The hardware completes transmission of eight data bits, receives the ninth bit during ACK clock period, and sets interrupt pending--keeping SMBus on hold and allowing the software to process the transfer results and check errors.
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Advance Information 13.8.2 Master Receive Mode In Master Receive Mode, the master addresses the slave by sending the slave address. After which, the master will receives data from the slave and then terminates the transfer after all data has been received.
Set SMSR - Write 90H to SMSR (This is done by software)
a) Write Slave Address to SDSR b) Set BSY bit in SMSR (=B0H) (This is done by software)
Generate START Condition Send SDSR data byte, receive ACK bit, set INT bit in SMCR (This is done by hardware)
Repeated Start (RS) entry from Figure 13-9
Last Data Byte received? (Done by software) NO a) Set ACKEN bit in SMCR b) Clear INT bit in SMCR (This is done by software)
YES
a) Clear ACKEN bit in SMCR b) Clear INT bit in SMCR (This is done by software)
Receive Data Byte in SDSR, sent NACK bit, set INT bit in SMCR (This done by hardware)
Receive Data Byte into SDSR, send ACK bit, set INT bit in SMCR (This is done by hardware)
Read received Data Byte from SDSR (This done by software)
Read received Data Byte from SDSR (This is done by software)
a) Clear BSY bit in SMSR (=90H) b) Clear INT bit in SMCR (This is done by software)
Generate STOP condition (This done by hardware)
END
1245 SMBus_Master_ReceiveMode.0
FIGURE
13-6: SMBus Master Receive Mode Operation
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Advance Information Figure 13-6 illustrates interaction between 8051 firmware and SMBus controller hardware in Master Receive mode: Master Receive mode: 1. Write 90H to SMSR. This will preset SMBus controller for Master Receive mode. 2. Write a 7-bit slave address to SDSR[7-1], and `1' to SDSR[0] (R/W# bit). The R/W# bit determines the direction of the transfer--if R/W# = 1 then the master will receive data from the slave. Set the BSY bit in SMSR register. SMBus controller will generate a START condition and automatically send SDSR data over the SMBus. 3. The hardware completes transmission of eight data bits, receives the ninth bit during ACK clock period, and sets interrupt pending. This keeps SMBus on hold and allows the software to process the transfer results and check errors. Note that in the case of successful transmission, allowing that arbitration has not failed, the slave is expected to send back an ACK to the master-- lowering the SDAn line during ACK clock. 4. Determine whether the next transfer is the last data byte to transfer from the slave. If not, set the ACK enable bit and clear the interrupt pending bit in SMCR to release the SMBus allowing the slave to send the next data byte to the master. Proceed to Step 5 to finish receiving the next data byte. If yes, indicated by only one byte remaining, clear the ACK enable bit and clear the interrupt pending bit in SMCR. This releases the SMBus allowing the slave to send the last data byte to the master. Proceed to Step 7 to complete receiving the last data byte. 5. The hardware completes receipt of eight data bits, then sends ninth bit during ACK clock period, and sets interrupt pending. This keeps SMBus on hold and allows the software to read the received byte. The data sent in ACK clock period depends on the value of ACKEN bit in SMCR register. If ACKEN bit is set, then ACK is generated automatically-- SDAn is `0' in the ACK clock period. 6. Read the received data byte from SDSR and return to Step 4. 7. The hardware completes receipt of eight data bits, sends ninth bit during ACK clock period, and sets interrupt pending. This keeps SMBus on hold and allows the software to read the received byte. The data sent in ACK clock period depends on the value of ACKEN bit in SMCR register. If ACKEN bit is cleared, then NACK is generated automatically--SDAn is floating = `1' in ACK clock period. 8. Read the last received data byte from SDSR, clear the BSY bit in SMSR, and then clear the interrupt pending bit in SMCR. The controller hardware will generate a STOP condition and release the SMBus channel which completes the transaction.
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Advance Information 13.8.3 Slave Transmit Mode In the Slave Transmit Mode, the slave compares the received address with SAR register contents. If the received address and SAR register matches, the slave will transmit data to the master until the master stops the transaction.
Set SMSR - Write 10H to SMSR (This is done by software)
Detect START condition and Receive Data Byte to SDSR (This is done by hardware)
SAR[7:1] matches SDSR[7:1]? (Done by hardware) YES Send ACK, set INT bit in SMCR Set MOD0 bit in SMSR (=70H) (This is done by hardware)
NO
Write data to SDSR (This is done by software)
Clear INT bit in SMCR (This is done by software)
Send SDSR Data Byte, Receive ACK bit; set INT bit in SMCR (This is done by hardware)
ACK
ACK received? (Done by software)
NACK a) Clear MOD0 bit in SMCR (=30H) b) Clear INT bit in SMCR (This is done by software) Detect STOP Condition (This done by hardware)
END
1245 SMBus_Slave_XmitMode.0
FIGURE
13-7: SMBus Slave Transmit Mode Operation
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Advance Information Figure 13-7 illustrates interaction between 8051 firmware and SMBus controller hardware in Slave Transmit mode: Slave Transmit mode: 1. Write 10H to SMSR. This will preset SMBus controller for Slave Receive mode. 2. The hardware detects the START bit, automatically sets the BSY bit, and receives the data byte from the bus. Then the hardware compares the value of SAR[7:1] with the data received in the SDSR[7:1]: If it matches, proceed to Step 3 to complete the address phase. If not, detect STOP condition when generated by the master. The STOP condition clears BSY bit in the hardware and completes the transaction. 3. The hardware sends ACK and sets the interrupt pending bit to keep SMBus on hold. If the value of the R/W# bit from the master (=SDSR[0]) is `1', then SMSRn_MOD0 is set and SMBus controller automatically switches to Slave Transmit mode. For example, when the master requires data from the slave. 4. Write data to be transmitted to the SDSR and clear the interrupt pending bit in SMCR. This causes the data in SDSR to be sent automatically over SMBus by controller hardware. 5. The hardware completes transmission of eight data bits, receives the ninth bit during ACK clock period, and sets interrupt pending. This keeps SMBus on hold and allows the software to process the transfer results and check errors. Note that in the case of successful transmission, allowing that arbitration has not failed, the master is expected to send back an ACK to the slave-- lowering the SDAn line during ACK clock--except for the last byte of the transaction. 6. Determine whether the last data byte has transmitted. If no, ACK was received. Return to Step 4 to start the next data byte transmit cycle. If yes, NACK was received. Clear SMSRn_MOD0 bit in SMSR register and clear the interrupt pending bit in SMCR. This will release the bus so that the master will be able to generate a STOP condition which clears BSY bit in hardware and completes the transaction.
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Advance Information 13.8.4 Slave Receive Mode In Slave Receive Mode, the slave compares the received address with the SAR register contents. If they match, the slave will receive data from the master until the master stops the transaction.
Set SMSR - Write 10H to SMSR (This is done by software)
Detect START condition and Receive Data Byte to SDSR (This is done by hardware)
SAR[7:1] matches SDSR[7:1]? (Done by hardware)
NO
YES Send ACK, set INT bit in SMCR Clear MOD0 bit in SMSR (=30H) (This is done by hardware) Detect STOP Condition (This is done by hardware)
a) Set ACKEN bit in SMCR b) Clear INT bit in SMCR (This is done by software)
Receive data to SDSR, send ACK bit, set INT bit in SMCR or Detect STOP (This is done by hardware)
STOP is detected? (Done by software)
YES
NO Read received data byte from SDSR (This is done by software) END
1245 SMBus_Slave_ReceiveMode.0
FIGURE
13-8: SMBus Slave Receive Mode Operation
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Advance Information Figure 13-8 illustrates interaction between 8051 firmware and SMBus controller hardware in Slave Receive mode: Slave Receive mode: 1. Write 0x10 to SMSR. This will preset SMBus controller for Slave Receive mode. 2. The hardware detects the START bit, automatically sets the BSY bit, and receives the data byte from the bus. Then the hardware compares the value of SAR[7:1] with the data received in the SDSR[7:1]: If it matches, proceed to Step 3 to complete the address phase. If not, detect STOP condition when generated by the master. The STOP condition clears BSY bit in the hardware and completes the transaction. 3. The hardware sends ACK and sets the interrupt pending bit to keep SMBus on hold. If the value of the R/W# bit from the master (=SDSR[0]) is `0', then SMSRn_MOD0 bit in SMSR is kept unchanged and SMBus controller is in Slave Receive Mode. This happen, for example, when the master sends data to the slave. 4. Set ACKEN bit and clear the interrupt pending bit to release the SMBus, allowing the master to send data byte to the slave. 5. If the master device stops the transaction, the hardware detects a STOP condition and clears BSY bit. OR If the master device continues sending data, the hardware completes transmission of eight data bits, receives the ninth bit during ACK clock period, and sets interrupt pending. This keeps SMBus on hold and allows the software to read the received byte. The data sent in ACK clock period depends on the value of ACKEN bit in SMCR register. If ACKEN bit is set, then ACK is generated automatically (SDAn is `0' in ACK clock period. 6. Determine whether the STOP bit is detected (BSY bit is cleared.) If no STOP condition is detected, go to Step 7 to read data. If master generates a STOP condition, then the transaction is complete. 7. Software reads the received data in SDSR and returns to Step 4 to start the next data byte receiving cycle.
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Advance Information 13.8.5 Switching Between Master Transmit and Master Receive Modes When switching from Master Transmit to Master Receive mode, a REPEATED START condition precedes the switch. This differs from most general mode switches when the switch occurs after a STOP condition and while the SMBus is idle. For example, when in Transmit Mode and after all necessary data is transmitted, the software writes a 7-bit slave address to SDSR[7:1] and `1' to the SDSR[0] (R/ W# bit). The software then clears the SMSRn_MOD0 bit in SMSR and clears the interrupt pending bit in SMCR to release the SMBus, which causes the controller hardware to generate a REPEATED START condition and the SMBus operation continues in Master Receive mode, see Figure 13-9. Refer to Section 13.5 for Master Transmit details and Section 13.6 Master Receive details.
Set SMSR - Write D0H to SMSR (This is done by software)
a) Write Slave Address to SDSR b) Set BSY bit in SMSR (=F0H) (This is done by software)
Generate START Condition (This is done by hardware)
Send SDSR data byte, Receive ACK bit; set INT bit in SMCR (This is done by hardware)
More Data to Transmit? (Done by software) YES Write new data to be transmitted to SDSR (This is done by software)
NO
a) Write Slave Address to SDSR b) Clear MOD0 bit in SMSR (=B0H) c) Clear INT bit in SMCR (This is done by software)
Generate REPEATED START (RS) condition. Send SDSR data byte, Receive ACK bit, Set INT bit in SMCR (This is done by hardware)
Clear INT bit in SMCR (This is done by software)
Continue Master Receive operations From RS entry on Figure 13-6
1245 SMBus_Xmit-ReceiveMode.0
FIGURE
13-9: SMBus Transmit/Receive Mode Switch
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Advance Information Figure 13-9 illustrates interaction between 8051 firmware and SMBus controller hardware in Master Transmit to Master Receive mode switch: Master Transmit Mode to Master Receive Mode Switch: 1. Write D0H to SMSR. This will preset SMBus controller for Master Transmit mode. 2. Write a 7-bit slave address to SDSR[7-1] and `0' to SDSR[0] (R/W# bit). The R/W# bit determines the direction of the transfer. For example, if R/W# = `0', then the master sends data to the slave. Set the BSY bit in the SMSR register. SMBus controller generates a START condition and automatically sends SDSR data over the SMBus. 3. The hardware completes the transmission of eight data bits, receives the ninth bit during ACK clock period, and sets the interrupt pending. This keeps SMBus on hold and allows the software to process the transfer results and check errors. Note: In the case of a successful transmission, allowing that arbitration has not failed, the slave is expected to send back an ACK to the master-- lowering the SDAn line during ACK clock. 4. Check for more data transfer. If the master has more data to transfer, the software will write the next data byte to SDSR and clear the interrupt pending bit in SMCR. This causes the data in SDSR to be sent automatically over the SMBus by controller hardware and returns to Step 3. If the master has no data to transfer, the software will write a 7-bit slave address to SDSR[7-1] and `1' to SDSR[0] (R/W# bit). The R/W# bit determines the direction of the transfer. For example, if R/W# = `1', then the master receives data from the slave. The software clears the SMSRn_MOD0 bit in SMSR and clears the interrupt pending bit in SMCR to release the SMBus. The controller hardware will generate a REPEATED START condition and the SMBus operation continues in Master Receive mode, see Figure 13-9. For Master Transmit details, see Section 13.5 For Master Receive details, see Section 13.6.
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Advance Information
14.0 PS/2 INTERFACE 14.1 PS/2 Features
* * * * * * * IBM PS/2 standard compliant Three independent PS/2 channels PS/2 hardware state machine for each channel Embedded transfer time-out detection Support both polling and interrupt driven operation Optional support for software bit-banging control Wake up from Idle and Power Down modes Each PS/2 channel consists of two signal lines: PS/2 clock (PSCLKn, n=0-2) and PS/2 data (PSDATn, n=0-2). The respective I/O buffers must have open drain outputs, so that either the SST79LF008 PS/2 host, or the PS/2 device can control PS/2 signals during bidirectional communications. However, the clock for both transmit and receive protocols is always generated by the PS/2 peripheral device. The PS/2 lines are connected externally to the positive 5V source via pull-up resistors (typically 10 KOhm). The on-chip PS/2 hardware state machine for each channel supports standard IBM PS/2 compliant receive and transmit protocols. Embedded PS/2 time-out detection frees core timers from PS/2 interface control. For any PS/2 transfer, start-bit interrupt as well as transfer completion interrupt are generated. The 8051 core controls PS/2 channels via memory mapped configuration registers. The PS/2 hardware state machine may be disabled. In this case, the respective PS/2 channel can operate in software controlled bit-banging mode. This allows communication to peripheral devices, which do not meet the standard PS/2 protocol timing.
14.2 PS/2 Channels
The PS/2 interface is an industry standard interface for PC communication to an external keyboard, mouse, internal pointing device, and other PS/2 compatible auxiliary devices. The SST79LF008 provides three identical PS/2 serial channels that are used to interface directly with PS/2 peripherals (see Figure 14-1).
PS/2 Channel 0 Hardware State Machine
PS/2 Channel 0 I/O Buffer
PSDAT0 PSCLK0
PS/2 Channel 1 Hardware State Machine
PS/2 Channel 1 I/O Buffer
PSDAT1 PSCLK1
PS/2 Channel 2 Hardware State Machine
PS/2 Channel 2 I/O Buffer
PSDAT2 PSCLK2
1245 PS2_ModBlockDia.0
FIGURE
14-1: PS/2 Module Block Diagram active PS/2 channel interrupt is cleared. If multiple start bits are detected at the same time from more than one channel, the lower order channel will be selected. If PS/2 hardware state machine is disabled, the PS2CRn_PS2_EN (n = 0-2) bit is cleared. It is the responsibility of the firmware to select the active receiving channel. The selection of transmitting channel is always controlled by the firmware.
Operations of all PS/2 channels are independent except for the following scenario. If PS/2 hardware state machine is enabled--the PS2CRn_PS2_EN (n=0-2) bit is set,see Section 14.4.3--only the channel which detects the start bit first is selected for receiving. The transfer over all other enabled channels is automatically inhibited by resetting the respective control registers to the default values, which results in forcing low state on the PS/2 clock lines. Software can set the PS2CRn_PS2_EN (n = 0-2) bits for the inhibited channels at any time, but hardware will hold clock lines low until the active channel completes receiving data and
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Advance Information
14.3 PS/2 Protocol Overview
The PS/2 protocol data stream transmits to/from the PS/2 device via each PS/2 channel consists of 11 bits: start bit (always 0), eight data bits (with least significant bit first), a parity bit (always odd parity), and a stop bit (always 1). The transmit protocol also includes a line control bit that serves as PS/2 device acknowledgement. Normally the PS/2 interface is in the idle state with both clock and data lines floating (i.e., pulled-up high by external resistors). The receive start bit is created by a high to low transition of the clock signal PSCLKn while the data signal PSDATn is held low as shown in Figure 14-2. After the start bit, the PS/2 interface is in the active receive state. In this state, the PS/2 peripheral device generates clock signal PSCLKn and sends PS/2 data on the data line PSDATn. The SST79LF008 PS/2 host samples each data bit on the falling edge of the clock. The eight data bits are followed by the odd parity bit and a stop bit which completes the transfer. The PS/2 transmit mode is initiated when the PS/2 host switches the PS/2 channel into the transmit idle, or requestto-send state. In this state the respective clock line PSCLKn is high while the data line PSDATn is forced low by the SST79LF008. In response the PS/2 device gener1st CLK 2nd CLK
ates a falling edge on the clock line while the data signal PSDATn is still low. This indicates the start bit for the transmission as shown in Figure 14-3. After the start bit, the PS/ 2 interface is in the active transmit state. In this state, the PS/2 peripheral device generates clock signal PSCLKn, but the PS/2 data on the data line PSDATn is sent by the PS/2 host. Each data bit is shifted out of the SST79LF008 host on the falling edge of the clock. The eight data bits are followed by an odd parity bit and a stop bit. Then, the PS/2 device forces data line low and generates one more clock, called line-control bit, to complete the transfer. When the PS/2 host is receiving data from the PS/2 peripheral device the data stream can be aborted by forcing the clock line of the respective channel low. If the PS/2 abort occurs prior to the falling edge of the 10th clock, then the received data is discarded and the peripheral device will retransmit it later. If the PS/2 abort occurs following the falling edge of the 10th clock, then the received data must be accepted by the host, as the peripheral device will not retransmit it. See IBM Personal System/2 Hardware Interface Technical Reference for more details on PS/2 protocol.
CLK
10th CLK
11th CLK
DATA
FIGURE
Start Bit
Bit 0
Parity Bit
Stop Bit
1245 PS2_ReceiveProt.0
14-2: PS/2 Receive Protocol
9th CLK
CLK
I/O Inhibit
1st CLK
2nd CLK
10th CLK
11th CLK
DATA
FIGURE
Start Bit
Bit 0
Line Control Bit Parity Bit Stop Bit
1245 PS2_XmitProt.0
14-3: PS/2 Transmit Protocol
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Advance Information
14.4 PS/2 MMCRs
There are five MMC registers associated with each PS/2 channel: PS/2 transmit register, PS/2 receive register, PS/2 control register, PS/2 status, and PS/2 alternate status registers. The transmit and receive registers are located at the same address. There are also two registers common for all channels: PS/2 time-out control register and PS/2 status 2 register. 14.4.1 PS/2 Transmit Registers PS/2 transmit registers are write-only registers. To transmit a data byte over the PS/2 interface by the PS/2 hardware, it must be written while the PS2CRn_PS2_EN, n=0-2,and PS2CRn_PS2_T/R, n=0-2 bits in the PS/2 14.4.1.1 PS/2 Transmit Register 0 (PS2TX0)
Location Write 7F41H Reset 7 PS2TX0 _7 0 6 PS2TX0 _6 0 5 PS2TX0 _5 0 4 PS2TX0 _4 0 3 PS2TX0 _3 0 2 PS2TX0 _2 0 1 PS2TX0 _1 0 0 PS2TX0 _0 0
control register and the PS2STSn_XMIT_IDLE bit in the PS2 status register, or Alternate PS2 status register are set. If any one of the three bits, are cleared, PS2CRn_PS2_EN, PS2_T/R, or PS2STSn_XMIT_IDLE, then the data written to the transmit register is ignored. When PS/2 transmission is initiated, the PS2STSn_XMIT_ IDLE, n=0-2, and APS2STSn_XMIT_IDLE, n=0-2, bits are automatically cleared. After successful completion of the transmission, the PS2STSn_XMIT_IDLE and APS2STSn_ XMIT_IDLE bits are set, and the PS2CRn_PS2_T/R bit is cleared in hardware. This automatically switches the respective PS/2 channel into the receive mode.
14.4.1.2 PS/2 Transmit Register 1 (PS2TX1)
Location Write 7F45H Reset 7 PS2TX1 _7 0 6 PS2TX1 _6 0 5 PS2TX1 _5 0 4 PS2TX1 _4 0 3 PS2TX1 _3 0 2 PS2TX1 _2 0 1 PS2TX1 _1 0 0 PS2TX1 _0 0
14.4.1.3 PS/2 Transmit Register 2 (PS2TX2)
Location Write 7F49H Reset 7 PS2TX2 _7 0 6 PS2TX2 _6 0 5 PS2TX2 _5 0 4 PS2TX2 _4 0 3 PS2TX2 _3 0 2 PS2TX2 _2 0 1 PS2TX2 _1 0 0 PS2TX2 _0 0
Symbol PS2TXn[7:0] 14.4.2 PS/2 Receive Registers
Function PS/2 transmit, write only, register bits (n = 0-2) Thus, data received over PS/2 interface can be read from the PS/2 receive register only when the PS2STSn_ RDATA_RDY or APS2STSn_RDATA_RDY (n=0-2) bits are set. Reading this register while the PS2STSn_RDATA_ RDY or APS2STSn_RDATA_RDY (n=0-2) bits are cleared always returns 0FFH. The PS2STSn_RDATA_RDY or APS2STSn_RDATA_ RDY bits must be cleared by reading the status register in order to allow the next PS/2 data reception or transmission.
PS/2 receive registers are read-only registers. When the PS2CRn_PS/2_EN (n = 0-2) bit is set and the PS2CRn_ PS/2_T/R (n = 0-2) is cleared, the PS/2 hardware state machine places data, received from the peripheral device, into the receive register at the end of a successful receipt of data. At the same time, the respective PS/2 clock line is forced low by the PS/2 hardware to inhibit any further PS/2 transmission, and the PS2STSn_RDATA_RDY or APS2STSn_RDATA_RDY (n = 0-2) bits inthe status register or alternate status register are set indicating that data is ready to be read by the software.
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Advance Information 14.4.2.1 PS/2 Receive Register 0 (PS2RCV0)
Location Read 7F41H Reset 7 6 5 4 3 2 1 0 PS2RCV0 _0 1 PS2RCV0 PS2RCV0 PS2RCV0 PS2RCV0 PS2RCV0 PS2RCV0 PS2RCV0 _7 _6 _5 _4 _3 _2 _1 1 1 1 1 1 1 1
14.4.2.2 PS/2 Receive Register 1 (PS2RCV1)
Location Read 7F45H Reset 7 6 5 4 3 2 1 0 PS2RCV1 _0 1 PS2RCV1 PS2RCV1 PS2RCV1 PS2RCV1 PS2RCV1 PS2RCV1 PS2RCV1 _7 _6 _5 _4 _3 _2 _1 1 1 1 1 1 1 1
14.4.2.3 PS/2 Receive Register 2 (PS2RCV2)
Location Read 7F49H Reset 7 6 5 4 3 2 1 0 PS2RCV2 _0 1 PS2RCV2 PS2RCV2 PS2RCV2 PS2RCV2 PS2RCV2 PS2RCV2 PS2RCV2 _7 _6 _5 _4 _3 _2 _1 1 1 1 1 1 1 1
Symbol PS2RCVn[7:0] 14.4.3 PS/2 Control Registers
Function PS/2 receive, read only, register bits (n = 0-2)
14.4.3.1 PS/2 Control Register 0 (PS2CR0)
Location Read 7F42H Write Reset 7 6 5 4 PS2CR0_ STOP0 0 3 PS2CR0_ PARITY1 0 2 PS2CR0_ PARITY0 0 1 PS2CR0_ PS2_EN 0 0 PS2CR0_ PS2_T/R 0 PS2CR0_ PS2CR0_ PS2CR0_ WR_CLK WR_DATA STOP1 0 1 0
14.4.3.2 PS/2 Control Register 1 (PS2CR1)
Location Read 7F46H Write Reset 7 6 5 4 PS2CR1_ STOP0 0 3 PS2CR1_ PARITY1 0 2 PS2CR1_ PARITY0 0 1 PS2CR1_ PS2_EN 0 0 PS2CR1_ PS2_T/R 0 PS2CR1_ PS2CR1_ PS2CR1_ WR_CLK WR_DATA STOP1 0 1 0
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Advance Information 14.4.3.3 PS/2 Control Register 2 (PS2CR2)
Location Read 7F4AH Write Reset 7 6 5 4 PS2CR2_ STOP0 0 3 PS2CR2_ PARITY1 0 2 PS2CR2_ PARITY0 0 1 PS2CR2_ PS2_EN 0 0 PS2CR2_ PS2_T/R 0 PS2CR2_ PS2CR2_ PS2CR2_ WR_CLK WR_DATA STOP1 0 1 0
Symbol PS2CRn_WR_CLK
PS2CRn_WR_DATA
PS2CRn_STOP[1:0]
PS2CRn_PARITY[1:0]
PS2CRn_PS2_EN
Function PS/2 clock line control bit (n = 0-2) When PS2CRn_PS2_EN = 0 (bit-banging enabled) 1: Float the respective PS/2 channel's PSCLKn pin 0: Drive "low" the respective PS/2 channel's PSCLKn pin When PS2CRn_PS2_EN = 1, this bit can be updated but has no effect on PSCLKn pin. Reading this bit always returns the written value. PS/2 data line control bit (n = 0-2) When PS2CRn_PS2_EN = 0 (bit-banging enabled) 1: = Float the respective PS/2 channel's PSDATn pin 0: = Drive "low" the respective PS/2 channel's PSDATn pin When PS2CRn_PS2_EN = 1, this bit can be updated, but has no effect on PSDATn pin. Reading this bit always returns the written value. PS/2 hardware state machine stop frame control bits. Valid only when PS2CRn_PS2_EN = 1. PS/2 transmit protocol with high level stop bit (n = 0-2) 00: PS/2 receive protocol with high level stop bit (PS/2 standard) 01: PS/2 receive protocol with low level stop bit 10: PS/2 receive protocol stop bit level is ignored (data for stop bit clock is not checked, however, it is still counted as the 11th clock of the receiving data stream). 11: Reserved PS/2 hardware state machine parity frame control bits. Valid only when PS2CRn_PS2_EN = 1. (n = 0-2) 00: PS/2 receive and transmit protocols with odd parity bit (PS/2 standard) 01: PS/2 receive and transmit protocols with even parity bit 10: PS/2 receive protocol parity bit level is ignored (data for parity bit clock is not checked, however, it is still counted as the 10th clock of the receiving data stream). PS/2 transmit protocol with odd parity bit 11: Reserved PS2 Channel hardware state machine Enable bit (n = 0-2) 1: Enable PS/2 hardware state machine. The PS/2 hardware automatically receives or transmits data over the respective PS/2 channel depending on the PS2CRn_PS2_T/R bit. 0: Disable PS/2 hardware state machine. Enable bit-banging of PSCLKn and PSDATn lines under software control using PS2CRn_WR_CLK and PS2CRn_WR_DATA bits in this register as well as (A)PS2STSn_RD_DATA and (A)PS2STSn_RD_CLK flags in the status register. When PS2CRn_PS2_EN bit switches from `0' to `1', the PS/2 hardware is enabled in receive or transmit mode depending on PS2CRn_PS2_T/R bit (default: receive mode with PS2CRn_PS2_T/R = 0). When PS2CRn_PS2_EN bit switches from `1' to `0', the PS/2 lines are set according to PS2CRn_WR_CLK and PS2CRn_WR_DATA values, and PS/2 hardware is disabled.
Note:To abort a transfer from the PS/2 peripheral, the PS2CRn_WR_CLK and PS2CRn_PS2_EN bits should be cleared simultaneously prior to the falling edge of the 10th clock in the receiving data stream (parity bit), and then held for at least 100S. If PS2CRn_PS2_EN bit is cleared after the falling edge of the 10th clock, then the received data is saved in the receive register (provided there is no parity error), (A)PS2STSn_RDATA_RDY bit is set, and PSCLKn line is forced low.
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Advance Information PS2CRn_PS2_T/R PS/2 Channel Transmit/Receive control bit. Valid only when PS2CRn_PS2_EN = 1. (n = 0-2) 1: Enable PS/2 channel to transmit data 0: Enable PS/2 channel to receive data Transmit: Setting the PS/2_T/R bit in software causes the PS/2 hardware to inhibit PS/2 interface (PSCLKn line is driven low and PSDATn line is floated). The channel is inhibited until the next write to the transmit register, which switches the PS/2 channel into request-to-send state (PSDATn line is driven low and after that the PSCLKn line is floated). In response, the PS/2 device starts transmission by generating PS/2 clock pulses. During the transmission, the peripheral device drives PSCLKn line and the PS/2 hardware drives PSDATn line until the stop bit is sent. Then the PS/2 device generates line control bit clock and data. The PS/2_T/ R bit is automatically cleared if transmit time-out is detected, or by the 11th clock rising edge when the line control bit successfully completes the transmission. In the latter case the PS/2 channel hardware automatically switches into receive mode. Receive: When PS2CRn_PS2_T/R bit is cleared in software or after successful transmission the PS/2 channel is in receive mode with PSCLKn and PSDATn lines floating and ready to automatically shift data from the peripheral PS/2 device.
Note:The PS2CRn_PS2_T/R bit must not be cleared by software in the middle of the transmission. The PS2CRn_PS2_T/R bit can be set by software in the middle of receiving data, prior to the falling edge of the 10th clock (parity bit). In this case the received data is discarded. If this bit is set after the 10th clock, the received data is saved in the receive register (provided no parity error), the (A)PS2STSn_RDATA_RDY bit is set, and PSCLKn line is forced low. Neither transmit nor receive operation is possible if any of the bits (A)PS2STSn_RDATA_RDY, (A)PS2STSn_T_TIMEOUT, or (A)PS2STn_R_TIMEOUT in the status register are set, because in these cases the channel's PSCLKn line will be held low until the status register is read by software.
14.4.4 PS/2 Status Registers There are six PS/2 status registers: one PS/2 Status Register and one Alternate PS/2 Status Register for each PS/2 channel. Reading the alternate status register, APS2STSn, does NOT clear the respective channel's interrupt sources and/or status bits. However, reading the status register, PS2STSn, clears PS/2 channel interrupt sources and the status bits PS2STSn_FE/APS2STSn_FE, n=0-2, 14.4.4.1 PS/2 Status Register 0 (PS2STS0)
Location Read 7F43H Write Reset 7 PS2STS0_ RD_CLK 0 6 PS2STS0_ RD_DATA 1 5 PS2STS0_T _TIMEOUT 0 4 PS2STS0_ XMIT_IDLE 1 3 PS2STS0_ FE 0 2 1 0 PS2STS0_ PS2STS0_R PS2STS0_R PE _TIMEOUT DATA_RDY 0 0 0
PS2STSn_PE/APS2STSn_PE, n=0-2, PS2STSn_ RDATA_RDY/APS2STSn_RDATA_RDY, n=0-2, PS2STSn _T_TIMEOUT/APS2STSn_T_TIMEOUT, n=0-2, PS2STSn_R_TIMEOUT/APS2STSn_R_TIMEOUT, n=0-2, PS2STSn_TXSB/APS2STSn_TXSB, n=0-2, and PS2STSn_RX_BUSY/APS2STSn_RX_BUSY, n=0-2, of the respective channel.
14.4.4.2 PS/2 Status Register 1 (PS2STS1)
Location Read 7F47H Write Reset 7 6 5 4 3 2 1 0 PS2STS1_ PS2STS1_ PS2STS1_T PS2STS1_X PS2STS1_ RD_CLK RD_DATA _TIMEOUT MIT_IDLE FE 0 1 0 1 0 PS2STS1_ PS2STS1_R PS2STS1_R PE _TIMEOUT DATA_RDY 0 0 0
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Advance Information 14.4.4.3 PS/2 Status Register 2 (PS2STS2)
Location Read 7F4BH Write Reset 7 6 5 4 3 2 1 0 PS2STS2_ PS2STS2_ PS2STS2_T PS2STS2_X PS2STS2_ PS2STS2_ PS2STS2_R PS2STS2_R RD_CLK RD_DATA _TIMEOUT MIT_IDLE FE PE _TIMEOUT DATA_RDY 0 1 0 1 0 0 0 0
14.4.4.4 Alternate PS/2 Status Register 0 (APS2STS0)
Location Read 7FF7H Write Reset 7 6 5 4 3 2 1 0 APS2STS0 APS2STS0 APS2STS0_ APS2STS0_ APS2STS0 APS2STS0 APS2STS0_ APS2STS0_ _RD_CLK _RD_DATA T_TIMEOUT XMIT_IDLE _FE _PE R_TIMEOUT RDATA_RDY 0 1 0 1 0 0 0 0
14.4.4.5 Alternate PS/2 Status Register 1 (APS2STS1)
Location Read 7FF8H Write Reset 7 6 5 4 3 2 1 0 APS2STS1 APS2STS1 APS2STS1_ APS2STS1_ APS2STS1 APS2STS1 APS2STS1_ APS2STS1_ _RD_CLK _RD_DATA T_TIMEOUT XMIT_IDLE _FE _PE R_TIMEOUT RDATA_RDY 0 1 0 1 0 0 0 0
14.4.4.6 Alternate PS/2 Status Register 2 (APS2STS2)
Location Read 7FF9H Write Reset 7 6 5 4 3 2 1 0 APS2STS2 APS2STS2 APS2STS2_ APS2STS2_ APS2STS2 APS2STS2 APS2STS2_ APS2STS2_ _RD_CLK _RD_DATA T_TIMEOUT XMIT_IDLE _FE _PE R_TIMEOUT RDATA_RDY 0 1 0 1 0 0 0 0
Symbol (A)PS2STSn_RD_CLK
Function Not implemented PS/2 clock line status flag (n = 0-2) This bit reflects the current state of the PSCLKn line. The RD_CLK flag can be used in conjunction with PS2CRn_WR_CLK control bit for software bit-banging when PS2CRn_PS2_EN = 0. A high to low transition on PSCLKn pin caused by the peripheral device will generate the following: * PS2 channel interrupt request in the INTSRCB register when PS2CRn_PS2_EN = 0 * PS2 start bit interrupt request in the WSRCA register, regardless of the PS2CRn_PS2_EN value.
Note:For proper bit-banging operations the (A)PS2STSn_RDATA_RDY, (A)PS2STn_R_TIMEOUT, and (A)PS2STSn_T_TIMEOUT flags in this registers must be cleared.
(A)PS2STSn_RD_DATA
PS/2 data line status flag (n = 0-2) This bit reflects the current state of the PSDATn line. The (A)PS2STSn_RD_DATA flag can be used in conjunction with PS2CRn_WR_DATA control bit for software bit-banging when PS2CRn_PS2_EN= 0 (A)PS2STSn_T_TIMEOUT Transmission Time-out flag (n = 0-2) This bit is set when PS2CRn_PS2_EN = 1, and one of the following conditions is detected:
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Advance Information * The transmission bit time (time between clock falling edges) exceeds 300s, if this time-out detection is enabled. * The transmission start clock is not received within 25 ms of signaling a transmission request event (request-to-send state), if this time-out detection is enabled. * The time from the 1st (start) clock falling edge to the rising edge of the 11th clock (line control bit) exceeds 2 ms, if this time-out detection is enabled. * The response start bit is not received within 25ms after successful completion of the transmission, if this time-out detection is enabled. The channel's PSCLKn pin is pulled down in hardware after the (A)PS2STSn_T_TIMEOUT bit is set and will be held low until (A)PS2STSn_T_TIMEOUT is cleared by reading the status register in software. The PS/2 channel interrupt request is generated on the low to high transition of (A)PS2STSn_T_TIMEOUT. (A)PS2STSn_XMIT_IDLE Transmitter idle status flag (n = 0-2) This bit is cleared by writing to the transmit register when the channel's hardware is in transmit mode (PS2CRn_PS2_EN = PS2CRn_PS2_T/R = 1). While (A)PS2STSn_XMIT_IDLE = 0, the PS/2 hardware state machine is transmitting data to the PS2 peripheral device. This bit is set when one of the following events occurs: * The rising edge of the 11th clock at the end of the successful transmission * Transmission time-out is detected ((A)PS2STSn_T_TIMEOUT is set) * When the PS2CRn_PS2_T/R bit is written `0' * When the PS2CRn_PS2_EN bit is written `0' If a transmission is completed successfully, the PS/2 channel will automatically switch into receiving mode. The PS/2 channel interrupt request is generated on the low to high transition of (A)PS2STSn_XMIT_IDLE. (A)PS2STSn_FE Framing Error flag (n = 0-2) This flag (along with (A)PS2STn_R_TIMEOUT) is set following the falling edge of the 11th clock when PS/2 channel is receiving data, and the stop bit level sampled on the falling edge of the 11th clock does not match the stop bit polarity specified in the control register. This flag is cleared by reading the status register. (A)PS2STSn_PE Parity Error flag (n = 0-2) This flag (along with (A)PS2STn_R_TIMEOUT) is set following the falling edge of the 10th clock when PS/2 channel is receiving data, and the parity bit level sampled on the falling edge of the 10th clock does not match either even or odd parity specified in the control register. This flag is cleared by reading the status register. (A)PS2STSn_R_TIMEOUT Receiving Time-out flag (n = 0-2) This bit is set when PS2CRn_PS2_EN = 1, and one of following conditions is detected: * The receiving bit time (time between clock falling edges) exceeds 300s, if this time-out detection is enabled * The time from the 1st (start) clock falling edge to the 11th (stop bit) clock falling edge exceeds 2 ms, if this time-out detection is enabled * Parity error (A)PS2STn_PE is detected * Framing error (A)PS2STSn_FE is detected The channel's PSCLKn pin is pulled down in hardware after the (A)PS2STn_R_TIMEOUT bit is set and will be held low until the (A)PS2STn_R_TIMEOUT bit is cleared by reading the status register in software. The PS/2 channel interrupt request is generated on the low to high transition of (A)PS2STn_R_TIMEOUT.
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Advance Information (A)PS2STSn_RDATA_RDY Received Data Ready flag (n = 0-2) If PS2CRn_PS2_EN = 1 and receive protocol is completed with no time-out, parity, or framing errors this bit is set following the falling edge of the 11th clock. It is also set when software attempts to abort current reception. This is done by clearing the PS2CRn_PS2_EN bit or setting the PS2CRn_PS2_T/R bit after the falling edge of the 10th clock. In any case, this bit indicates that the PS/2 receive register contains the data received from the PS/2 device. The channel's PSCLKn pin is pulled down in hardware after the (A)PS2STSn_RDATA_RDY bit is set and will be held low until the (A)PS2STSn_RDATA_RDY bit is cleared by reading the status register in software. The PS/2 channel interrupt request is generated on the low to high transition of (A)PS2STSn_RDATA_RDY. 14.4.5 PS/2 Time-out and Status 2 Registers The PS/2 Time-out control register is used to enable or disable PS/2 protocol time-out detection. 14.4.5.1 PS/2 Time-out Control Register (PS2TMOUT)
Location Read 7F44H Write Reset X X X X 0 7 6 5 4 3 TXTMSEL 2 TMRSPEN 0 1 TMOUTE N1 0 0 TMOUTEN0 0
Symbol X TXTMSEL
TMRSPEN
TMOUTEN1
TMOUTEN0
Function Not implemented Not defined Transmit 2ms Time-out selection bit 1: Enable in transmit mode, 2ms time-out is from the start bit falling edge to the line control bit clock rising edge 0: Disable in transmit mode, 2ms time-out is from the start bit falling edge to the line control bit data falling edge. Enable 25ms Response Time-out detection bit 1: Enable response time-out detection after successful transmit completion 0: Disable response time-out detection after successful transmit completion Enable 2ms and 25ms Time-out detection bit 1: Enable 2ms time-out detection for transmit/receive and 25ms time-out for transmit only 0: Disable 2ms time-out detection for transmit/receive and 25ms time-out for transmit only In transmit mode, a 2ms time-out is applied to the time interval from the start bit falling edge to the line control bit data, or clock edges, depending on the value of TXTMSEL. A 25ms time-out is applied to the time interval from the request-tosend state to the transmission start bit falling edge. In receive mode, 2ms time-out is applied to the time interval from the start bit falling edge to the stop bit falling edge. Enable 300us bit transfer Time-out detection bit 1: Enable bit transfer 300ss time-out detection for transmit/receive 0: Disable bit transfer 300s time-out detection for transmit/receive.
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Advance Information 14.4.5.2 PS/2 Status 2 Register (PS2STATUS2) The PS/2 Status 2 register is used to provide auxiliary status flags for all three PS/2 channels.
Location Read 7F48H Write Reset 0 0 0 7 TxSB2 6 TxSB1 5 TxSB0 4 RX_BUS Y2 0 3 RX_BUS Y1 0 2 RX_BUS Y0 0 1 TxRsp 0 X 0 -
Symbol X TxSB[2:0]
RX_BUSY[2:0]
TxRsp
Function Not implemented Not defined PS/2 channels 2-0 Transmit Start Bit Time-out flag This bit is set when the transmission start bit is not detected within 25 ms of the signal of a request-to-send state. This bit is cleared by reading the respective status register. PS/2 channel 2-0 Receiver Busy flag This bit is set when the start bit is received from the peripheral device. This bit is cleared by reading the respective status register. To avoid line contention, the software should not start transmission while the respective channel receives data from the PS/2 device and the RX_BUSY bit is `1'. See also the PS2CRn_PS2_T/R bit description on page 183. PS/2 Response Time-out flag This bit is set when no response start bit is detected within 25ms after completion of a successful transmission. This bit is cleared by reading any channel's status register.
Note:All PS/2 channel interrupt sources and the related status bits only can be cleared by reading the status register (PS2STS0, PS2STS1 or PS2STS2) of the respective channel. Neither interrupts nor status bits are affected by reading alternate status registers.
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Advance Information
15.0 FAN TACHOMETERS 15.1 Fan Tachometer Features
* * * * * * * 8-bit resolution Two independent channels Clock prescaler Programmable preload value Threshold detector Support for both polling and interrupt driven operation Wake up from Idle and Power Down modes fan speed and also detect when a fan has seized. Fan tachometer input pins are FAN1 and FAN2. These pins are multiplexed with GPIO24 and GPIO25 respectively. Tachometers use the 32.768 KHz oscillator clock as the time base source. The clock can be pre-scaled before being presented to a tachometer. On each rising edge of the FANn input, the preload value of the respective tachometer will be loaded into the 8 bit counter. The tachometer counter will then count up at each rising edge of the prescaled clock. A tachometer interrupt is generated if the counter reaches count C0H (192 decimal).
The SST79LF008 has two independent pulse counters gated by external signals. The most common application for these counters is fan tachometer, where the external gate signal is a square wave signal from the fan, with its frequency proportional to the fan speed. By measuring the period of the square wave, a fan tachometer can monitor a
15.2 Fan Tachometer Operation
Each fan tachometer includes a Clock Prescaler, a Pulse Counter, a Preload register, a Read Latch, and a Threshold Detector. See Figure 15-1.
Preload Register
32 kHz FANn
Clock Prescaler Load
Pulse Counter
Threshold Detector
FANn Interrupt
Latch
Read Latch
1245 FanTach_BlockDia.0
FIGURE
15-1: Fan Tachometer Block Diagram ister. Hence, the pulse count can be scaled so that the threshold value corresponds to the desired lower limit of the fan speed. The preload value should be equal to 192 less the pulse count for the fan speed lower limit. The counter is re-loaded with the preload value automatically on the FANn input signal rising edge, or when the software is writing to the preload register. Since software operations are asynchronous to the FANn signal, the tachometer reading may be incorrect until the second FANn rising edge after the write to the preload register. When the pulse count equals or exceeds the threshold value, the respective FANn interrupt request is generated. The interrupt is cleared when preload register is written with the value below threshold. The fan tachometers continue running in the Idle mode. Operation in the Power Down mode is controlled by software as shown Section 15.3.
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The clock prescaler provides the fan tachometer time base. The frequency of the prescaler output clock is equal to 32.768 KHz times the prescaler ratio (1/2 by default). The prescaler ratio for each channel can be independently specified via a prescaler register from 1/1 to 1/8, which accommodates fans with a wide range of speed. The prescaler output pulses are counted by the pulse counter during the FANn input signal period. The counter is incremented on the rising edge of the prescaler clock, and it does not wrap around when the maximum FFH (255 decimal) count is reached. On the rising edge of the FANn signal, the pulse counter value is latched into the read latch and the preload value is loaded into the pulse counter. Thus, the read latch contains the measurement of the last input signal period in time base units. The threshold value for the fan speed threshold detector is fixed at C0H (192 decimal) count. However, the initial value for the pulse counter is programmable via the preload reg(c)2006 Silicon Storage Technology, Inc.
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Advance Information
15.3 Fan Tachometers MMCRs
15.3.1 Fan Tachometer 1 Read Register (FANCNT1)
Location Read 7FBAH Write Reset 7 6 5 4 3 2 1 0 FANCNT1 _0 0 FANCNT1 FANCNT1 FANCNT1 FANCNT1 FANCNT1 FANCNT1 FANCNT1 _7 _6 _5 _4 _3 _2 _1 0 0 0 0 0 0 0
Symbol FANCNT1[7:0]
Function Not implemented Read-only register which returns the last latched Fan Tachometer 1 pulse count
15.3.2 Fan Tachometer 2 Read Register (FANCNT2)
Location Read 7FBBH Write Reset 7 6 5 4 3 2 1 0 FANCNT2 _0 0 FANCNT2 FANCNT2 FANCNT2 FANCNT2 FANCNT2 FANCNT2 FANCNT2 _7 _6 _5 _4 _3 _2 _1 0 0 0 0 0 0 0
Symbol FANCNT2[7:0]
Function Not implemented Read-only register which returns the last latched Fan Tachometer 2 pulse count
15.3.3 Fan Tachometer 1 Preload Register (FAN1LD)
Location Read 7FBCH Write Reset 7 FAN1LD _7 0 6 FAN1LD _6 0 5 FAN1LD _5 0 4 FAN1LD _4 0 3 FAN1LD _3 0 2 FAN1LD _2 0 1 FAN1LD _1 0 0 FAN1LD _0 0
Symbol FAN1LD[7:0]
Function Preload value for Fan Tachometer 1 pulse counter. Pulse counter is loaded with this value when the preload register is written to by 8051 firmware, and each time on the rising edge of FAN1 input.
15.3.4 Fan Tachometer 2 Preload Register (FAN2LD)
Location Read 7FBDH Write Reset 7 FAN2LD _7 0 6 FAN2LD _6 0 5 FAN2LD _5 0 4 FAN2LD _4 0 3 FAN2LD _3 0 2 FAN2LD _2 0 1 FAN2LD _1 0 0 FAN2LD _0 0
Symbol FAN2LD[7:0]
Function Preload value for Fan Tachometer 2 pulse counter. Pulse counter is loaded with this value when the preload register is written to by 8051 firmware, and each time on the rising edge of FAN2 input.
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Advance Information 15.3.5 Fan Tachometer Prescaler Register (FANTIMEBASE)
Location Read 7FBEH Write Reset 7 6 5 X 4 X 3 F2S1 0 2 F2S0 1 1 F1S1 0 0 F1S0 1 F2STOPE F1STOPE N N 0 0
Symbol X F2STOPEN
F1STOPEN
F2S1, F2S0
F1S1, F1S0
Function Not implemented Not defined Fan Tachometer 2 operation in Power Down mode control bit 1: Tachometer 2 keeps running when 8051 enters into Power Down mode 0: Tachometer 2 is stopped and loaded with preload value when 8051 enters into Power Down mode Fan Tachometer 1 operation in Power Down mode control bit 1: Tachometer 1 keeps running when 8051 enters into Power Down mode 0: Tachometer 1 is stopped and loaded with preload value when 8051 enters into Power Down mode Fan Tachometer 2 Prescaler ratio 00: prescaler ratio = 1/1 01: prescaler ratio = 1/2 10: prescaler ratio = 1/4 11: prescaler ratio = 1/8 Fan Tachometer 1 Prescaler ratio 00: prescaler ratio = 1/1 01: prescaler ratio = 1/2 10: prescaler ratio = 1/4 11: prescaler ratio = 1/8
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Advance Information
16.0 ANALOG TO DIGITAL CONVERTER (ADC) 16.1 ADC Features
* * * 10-bit resolution Eight input channels Two conversion modes - Single mode: one-time A/D conversion of one channel - Continuous mode: continuous cyclical conversion on one to four channels Sample-and-hold input circuit A/D interrupt requested at the end of conversion Standby mode with low power consumption Automatic entry into standby mode when 8051 is in Power Down mode An ADC block diagram is shown in Figure 16-1. In addition to being the analog power supply voltage, AVDD is also used as the reference voltage for the A/D conversion. There are five 8-bit data registers that store up to four conversion results simultaneously. The eight analog input pins are divided into two groups: group 0 (ACH0 to ACH3), and group 1 (ACH4 to ACH7). Table 16-1specifies the relation between analog input channels and data registers.
* * * *
TABLE 16-1: Analog Input Channels/Data Registers relationship
GROUP0 ACH0 ACH1 ACH2 ACH3 GROUP1 ACH4 ACH5 ACH6 ACH7 ADC Data Register ADDRA[7:0]:ADDRL[1:0] ADDRB[7:0]:ADDRL[3:2] ADDRC[7:0]:ADDRL[5:4] ADDRD[7:0]:ADDRL[7:6]
T16-1.0 1320
Module Data Bus Bus Interface
Internal Data Bus
ADDRC
ADDRD
ADDRA
ADDRB
10-bit D/A AVSS
ACH0 ACH1 ACH2 ACH3 ACH4 ACH5 ACH6 ACH7 Legend:
Analog Multiplexer
ADCSR
ADDRL
AVDD
Successiveapproximations register
FCCLK/12 Comparator Sample-andhold circuit Control Circuit FCCLK/24
ADC Interrupt Signal
ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D ADDRL: A/D data register low bits
1245 ADC_BlkDiag.0
FIGURE
16-1: ADC Block Diagram
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Advance Information
16.2 ADC MMCRs
There are six 8-bit read only A/D data registers that are used to store the A/D conversion results. 16.2.1 ADC Data register A (ADDRA)
Location Read 7F8EH Write Reset 7 AD9 0 6 AD8 0 5 AD7 0 4 AD6 0 3 AD5 0 2 AD4 0 1 AD3 0 0 AD2 0
Symbol AD[9:2]
Function Not implemented The most significant 8 bits of A/D conversion result for channel ACH0 or ACH4
16.2.2 ADC Data Register B (ADDRB)
Location Read 7F8FH Write Reset 7 BD9 0 6 BD8 0 5 BD7 0 4 BD6 0 3 BD5 0 2 BD4 0 1 BD3 0 0 BD2 0
Symbol BD[9:2]
Function Not implemented The most significant 8 bits of A/D conversion result for channel ACH1 or ACH5
16.2.3 ADC Data Register C (ADDRC)
Location Read 7F90H Write Reset 7 CD9 0 6 CD8 0 5 CD7 0 4 CD6 0 3 CD5 0 2 CD4 0 1 CD3 0 0 CD2 0
Symbol CD[9:2]
Function Not implemented The most significant 8 bits of A/D conversion result for channel ACH2 or ACH6
16.2.4 ADC Data Register D (ADDRD)
Location Read 7F91H Write Reset 7 DD9 0 6 DD8 0 5 DD7 0 4 DD6 0 3 DD5 0 2 DD4 0 1 DD3 0 0 DD2 0
Symbol DD[9:2]
Function Not implemented The most significant 8 bits of A/D conversion result for channel ACH3 or ACH7
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Advance Information 16.2.5 ADC Data Register Lower Bits (ADDRL)
Location Read 7F92H Write Reset 7 DD1 0 6 DD0 0 5 CD1 0 4 CD0 0 3 BD1 0 2 BD0 0 1 AD1 0 0 AD0 0
Symbol DD[1:0] CD[1:0] BD[1:0] AD[1:0]
Function Not implemented The least significant 2 bits of A/D conversion result for channel ACH3 or ACH7 (the most significant 8 bits of A/D conversion result are stored in register ADDRD) The least significant 2 bits of A/D conversion result for channel ACH2 or ACH6 (the most significant 8 bits of A/D conversion result are stored in register ADDRC) The least significant 2 bits of A/D conversion result for channel ACH1 or ACH5 (the most significant 8 bits of A/D conversion result are stored in register ADDRB) The least significant 2 bits of A/D conversion result for channel ACH0 or ACH4 (the most significant 8 bits of A/D conversion result are stored in register ADDRA)
16.2.6 ADC Control and Status Register (ADCSR)
Location Read 7F93H Write Reset 0 0 0 0 0 0 0 0 7 ADF 6 ADCEN 5 ADST 4 SCAN 3 CKS 2 CH2 1 CH1 0 CH0
Symbol ADF
ADCEN
ADST
SCAN
CKS
CH[2:0]
Function A/D conversion completion flag Set by hardware in single mode when A/D conversion for the selected channel is completed. Set by hardware in continuous mode when A/D conversion cycle for all selected channels is completed. After ADF is set, the software must read ADCSR register first, then write 0 to ADF in order to clear this bit. Writing 1 to ADF bit will be ignored. Enable ADC bit 1: Enable ADC 0: Disable ADC, and switch ADC into standby mode If this bit is set, ADC enters/exits standby mode automatically when 8051 enters/ exits Power Down mode. A/D conversion Start bit 1: ADC conversion is started (in progress) 0: ADC conversion is stopped This bit can be set or cleared by software in either single or continuous mode. It is cleared by hardware when conversion is completed in single mode only. The ADST bit is also automatically cleared when ADCEN bit is cleared. A/D conversion mode selection bit 1: Continuous mode 0: Single mode A/D clock selection bit (A/D conversion time = 5 periods of ADC clock) 1: The frequency of ADC clock is FCCLK/12, FCCLK - 8051 core clock frequency 0: The frequency of ADC clock is FCCLK /24, FCCLK - 8051 core clock frequency Note: ADC clock frequency must not exceed 2.0 MHz Analog input channels selection bits
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Advance Information
16.3 ADC Operations
ADC implements a successive approximation algorithm with 10-bit resolution. It has two operating modes: single mode and continuous mode. To prevent incorrect results of the A/D conversion, the conversion mode, clock, and channel selection bits must be changed only when conversion is TABLE 16-2: Channel and Mode Selection
Group selection bit CH2 0 Channel selection bits CH1 0 1 1 0 1 CH0 0 1 0 1 0 1 0 1 Selected Input channels Single mode ACH0 ACH1 ACH2 ACH3 ACH4 ACH5 ACH6 ACH7 Continuous mode ACH0 ACH0-ACH1 ACH0-ACH2 ACH0-ACH3 ACH4 ACH4-ACH5 ACH4-ACH6 ACH4-ACH7
T16-2.0 1320
stopped (ADST = 0). It is acceptable to simultaneously write new values for the selection bits and to set the ADST bit in order to start a conversion.
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Advance Information 16.3.1 Single Mode Single mode is used only when a one-time A/D conversion on one channel is required. A typical, single mode conversion, with channel 1 (ACH1) selected, is described below. It is assumed that ADC is enabled (ADCEN = 1). 1. The software enables the A/D interrupt (ADCINTMSK = 1), selects a single mode (SCAN = 0) with ACH1 as the input channel (CH2 = CH1 = 0, CH0 = 1), and starts the A/D conversation (ADST = 1). 2. When the A/D conversion is complete, the result is transferred by hardware into ADDRB and ADDRL[3:2] registers. Simultaneously, the ADF flag is set to 1, the ADST bit is cleared to 0, and the ADC is stopped. 3. An ADC interrupt is generated since ADF = 1 and ADCINTMSK = 1. 4. In response to the ADC interrupt, the software interrupt service routine reads ADCSR, and then writes 0 in the ADF flag. After which, the software reads and processes, if necessary, the conversion result for the ACH1 channel. Using the software, the ADST bit can be set to 1 to start the next A/D conversion, and steps 2 through 4 are repeated. See Figure 16-2 for a timing diagram of this example.
Set* ADCINTMSK A/D Conversion starts ADST Clear* ADF Clear* Set* Set*
State of Channel 0 ACH0 State of Channel 1 ACH1 State of Channel 2 ACH2 State of Channel 3 ACH3
Idle
Idle
A/D Conversion (1)
Idle
A/D Conversion (2)
Idle
Idle
Idle
ADDRA Read Conversion Result* ADDRB A/D Conversion Result (1) A/D Conversion Result (2)
ADDRC
ADDRD NOTE: * Vertical arrows ( ) indicate instructions executed by software.
1245 ADC_OpSingle.0
FIGURE
16-2: Example of ADC Operation (Single Mode)
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Advance Information 16.3.2 Continuous Mode Continuous mode is used to monitor analog inputs in a group of channels, with up to four channels per group. When the software sets the ADST bit to 1, the A/D conversion starts with the first channel in the group (ACH0 when CH2 = 0, ACH4 when CH2 = 1). If two or more channels are selected, the conversion of the second channel (ACH1 or ACH5) starts immediately after the conversion of the first channel is complete. The A/D conversion continues cyclically on all selected channels until the ADST bit is cleared to 0 by the software. The conversion results are stored in the ADC data registers. A typical continuous mode conversion, with three channels in group 0 (ACH0 to ACH2) selected, is described below. It is assumed that ADC is already enabled (ADCEN = 1). 1. The software enables the A/D interrupt (ADCINTMSK = 1), selects continuous mode (SCAN = 1), and scans group 0 (CH2 = 0) with input channels ACH0 to ACH2 (CH1 = 1, CH0 = 0), and then starts the A/D conversion (ADST = 1). 2. After the A/D conversion of the first channel (ACH0) is complete, the conversion result is transferred by hardware to ADDRA and ADDRL[1:0] registers. 3. The conversion of the second channel (ACH1) is started automatically and the results are stored in ADDRC and ADDRL[3:2] registers. 4. The conversion cycle proceeds similarly for the third channel (ACH2) with results stored in ADDRC and ADDRL[5:4] registers. When the conversion of all selected channels (ACH0 through ACH2) is complete, the ADF flag is set to 1 and the conversion of the first channel (ACH0 starts again from step 2. 5. An ADC interrupt is generated because ADF = 1 and ADCINTMSK = 1. 6. In response to the ADC interrupt, the software reads ADCSR and writes 0 in the ADF flag. After which, the software reads and processes, if necessary, the conversion results for the three selected channels. 7. If the ADST bit remains set to 1, steps 2 through 6 are repeated automatically. When the ADST bit is cleared to zero in the software, the A/D conversion stops. Using the software, the ADST bit can be set to 1 to restart the A/D conversion cycle from the first channel (ACH0), beginning with step 2. See Figure 16-3 for a timing diagram of this example.
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Advance Information
Continuous A/D Conversion Set1 ADST Clear1 ADF A/D Conversion Time State of Channel 0 ACH0 State of Channel 1 ACH1 State of Channel 2 ACH2 State of Channel 3 ACH3 Transfer ADDRA ADDRB ADDRC ADDRD 1. Vertical arrows ( ) indicate instructions executed by software. 2. Currently being converted is ignored.
1245 ADC_OpContinuous.0
Clear1
Idle
A/D Conversion (1)
Idle
A/D Conversion (4)
Idle
Idle
A/D Conversion (2)
Idle
A/D Conversion (5) 2 Idle
Idle
A/D Conversion (3)
Idle
Idle
A/D Conversion Result (1)
A/D Conversion Result (4)
A/D Conversion Result (2)
A/D Conversion Result (3)
FIGURE
16-3: Example of ADC Operation (Continuous Mode)
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Advance Information
17.0 DIGITAL TO ANALOG CONVERTOR (DAC) 17.1 DAC Features
* * * * * * 8-bit resolution Four D/A channels with one shared R-string (resistor ladder network) converter Sample-and-hold output circuits Independent enable/disable control for each channel 0V output for disabled channel Standby mode with low power consumption (all channels and shared R-string converter are disabled) Automatic entry into standby mode when 8051 is in Power Down mode The DAC has one R-string digital-to-analog converter shared by 4 channels, see Figure 17-1. Each DAC channel generates an 8-bit resolution output and drives the corresponding output pin DAC0 to DAC3 via the sample-andhold circuit. The output voltage is determined by the value written to the respective DAC data register when the DAC channel is enabled. The output voltage is 0V, regardless of the value in the respective DAC data register, when the DAC channel is disabled to reduce power consumption. After reset and in power down mode, all four channels, as well as the shared R-string, are disabled and the voltages on the DAC0-3 outputs are 0V. AVDD analog power supply voltage is the reference voltage of the converter.
*
DACEN
R-String
Sample &Hold 0 SEL
DAC0
DACDAT0 DACDAT1 DACDAT2 DACDAT3 8 Level Shifter Decoder
Sample &Hold 1 SEL
DAC1
Sample &Hold 2 SEL
DAC2
DACCTRL[3:0]
Sample &Hold 3 SEL
DAC3
1245 DACblkdia.0
FIGURE
17-1: DAC Block Diagram
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Advance Information
17.2 DAC MMCRs
17.2.1 DAC Data Channel Register 0 (DACDAT0)
Location Read 7F4CH Write Reset 7 DACDAT0 _7 0 6 DACDAT0 _6 0 5 DACDAT0 _5 0 4 DACDAT0 _4 0 3 DACDAT0 _3 0 2 DACDAT0 _2 0 1 DACDAT0 _1 0 0 DACDAT0 _0 0
Symbol DACDAT0[7:0]
Function DAC channel 0 input data
17.2.2 DAC Data Channel Register 1 (DACDAT1)
Location Read 7F4DH Write Reset 7 DACDAT1 _7 0 6 DACDAT1 _6 0 5 DACDAT1 _5 0 4 DACDAT1 _4 0 3 DACDAT1 _3 0 2 DACDAT1 _2 0 1 DACDAT1 _1 0 0 DACDAT1 _0 0
Symbol DACDAT1[7:0]
Function DAC channel 1 input data
17.2.3 DAC Data Channel Register 2 (DACDAT2)
Location Read 7F4EH Write Reset 7 DACDAT2 _7 0 6 DACDAT2 _6 0 5 DACDAT2 _5 0 4 DACDAT2 _4 0 3 DACDAT2 _3 0 2 DACDAT2 _2 0 1 DACDAT2 _1 0 0 DACDAT2 _0 0
Symbol DACDAT2[7:0]
Function DAC channel 2 input data
17.2.4 DAC Data Channel Register 3 (DACDAT3)
Location Read 7F4FH Write Reset 7 DACDAT3 _7 0 6 DACDAT3 _6 0 5 DACDAT3 _5 0 4 DACDAT3 _4 0 3 DACDAT3 _3 0 2 DACDAT3 _2 0 1 DACDAT3 _1 0 0 DACDAT3_ 0 0
Symbol DACDAT3[7:0]
Function DAC channel 3 input data
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Advance Information 17.2.5 DAC Control Register (DACCTRL)
Location Read 7F50H Write Reset 0 0 0 0 0 0 0 0 7 6 5 4 DACEN 3 DACEN3 2 DACEN2 1 DACEN1 0 DACEN0
Symbol DACEN
DACEN3
DACEN2
DACEN1
DACEN0
Function DAC R-string Enable bit 1: Enable DAC R-string 0: Disable DAC R-string (standby mode DAC0-DAC3 output voltage is 0V) If this bit is set, DAC also enters/exits standby mode automatically when 8051 enters/exits Power Down mode. DAC Channel 3 Enable bit 1: Enable - DAC3 output voltage level is specified by the value in DACDAT3 register 0: Disable - DAC3 output voltage is 0V DAC Channel 2 Enable bit 1: Enable - DAC2 output voltage level is specified by the value in DACDAT2 register 0: Disable - DAC2 output voltage is 0V DAC Channel 1 Enable bit 1: Enable - DAC1 output voltage level is specified by the value in DACDAT1 register 0: Disable - DAC1 output voltage is 0V DAC Channel 0 Enable bit 1: Enable - DAC0 output voltage level is specified by the value in DACDAT0 register 0: Disable - DAC0 output voltage is 0V.
17.3 DAC Operations
17.3.1 Output Voltage For each channel, the DAC converts the input digital value stored in the respective DAC data register into an analog output voltage, relative to the analog ground pin (AVSS). The analog power supply voltage AVDD is used as the reference voltage of the converter. The output voltage level on DACn pin for enabled channel n = 0-3 can be found as follows: VOUT = (DACDATn[7:0]) * (AVDD / 256) 17.3.2 Conversion Cycle Since there is only one R-string, an interleaving scheme is used to periodically convert each of the DAC data registers and refresh the DAC output Sample-and-hold circuits. When a DAC channel is selected for conversion, the content of the respective data register is copied into an 8-bit intermediate register, which holds the value throughout the entire conversion time slot allocated for this channel. At the end of the conversion time the corresponding DAC Sample-and-hold circuit is updated. Each channel is allocated 24 core clocks for D/A conversion. A disabled channel will not be converted, but it will still occupy its time slot. Hence, the total conversion cycle for all 4 channels always occupies 96 core clock periods, i.e., conversion cycle time is equal to (96 * TCCLK.). 17.3.3 DAC Channel Control After SST79LF008 chip reset, the R-string and all DAC channels are disabled (DACCTRL register is cleared to 00H). In this state, no D/A conversion is performed, and the DAC is in standby mode with minimum current consumption. The shared DAC R-string is enabled via the DACEN bit in the DACCTRL register. Each DAC channel can be enabled by setting the corresponding DACENn (n = 0 to 3) bit in the DACCTRL register. Once the DAC channel is enabled, D/A converter outputs the voltage level, which is specified by the respective data register DACDATn.
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Advance Information Each DAC channel can be independently disabled by clearing the DACENn bit in the DACCTRL register. If the DAC channel is disabled, its output voltage is 0V regardless of the value stored in the channel's data register. 17.3.4 Standby Mode The DAC standby mode, with all DAC channels and the shared R-string disabled, provides the minimum possible DAC power consumption. All DAC0-DAC3 output voltages are forced to 0V in the standby mode. The DAC switches to the standby mode automatically, when 8051 is in Power Down mode. This happens regardless of the state of the DACENn bits in the DACCTRL register.
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Advance Information
18.0 KEYBOARD CONTROLLER HOST INTERFACE 18.1 Keyboard Controller Interface Overview
The SST79LF008 provides a 8042-style keyboard controller (KBC) host interface which is accessible via an LPC bus at standard I/O addresses 60H and 64H. This guarantees compatibility with the PC system BIOS and OS keyboard/ mouse services, as well as with any legacy applications that access keyboard ports directly. The KBC interface includes the following 8-bit registers: KBC data write register, KBC data read register, KBC comTABLE 18-1: Keyboard Controller Interface Mapping
LPC Host I/O Address and Access Type Address1 60H Access Write Read Write 64H Read Host-to-KBC data write Host-from-KBC data read Host-to-KBC command write Host-from-KBC status read Function 8051 Memory mapped Address and Access Type Access Read Write Read Write/Read Address (MMCR register) 7FF1H (KBCDATA) 7FF1H (KBCDATA) or 7FFAH (AUXDATA) 7FF1H (KBCDATA) 7FF2H (KBCSTS)
T18-1.1320
mand write register, and KBC status register. The host processor accesses KBC interface registers at two addresses in the LPC I/O space. The 8051 core accesses the KBC interface registers at three addresses in external data memory space. Table 18-1 describes the register mapping to the host I/O space and 8051 memory space, as well as the access type for each register.
1. The default base address for KBC host interface ports can be changed via SST79LF008 configuration registers (see Section 23). For simplicity the description in Section 18.1 refers to default addresses.
When the Host writes a command byte to the KBC through port 64H, this sets the C/D bit in the KBC status register and the IBF bit in the KBC status register. When the Host writes a data byte to the KBC through port 60H, this clears the C/D bit in the KBC status register and sets the IBF bit in the KBC status register. When the Host reads data from the KBC through port 60H, the OBF bit in the KBC status
register is cleared. See detailed bit description for the KBC status register in the next section. The KBC interface also includes a mechanism for the generation of IRQ1 and IRQ12 interrupts to the LPC Host when data from the keyboard or mouse is ready to be read by the system.
18.2 Keyboard Controller Interface MMCRs
18.2.1 Keyboard Data Register (KBCDATA)
Location Read 7FF1H Write Reset 7 KBCDATA _7 0 6 KBCDATA _6 0 5 KBCDATA _5 0 4 KBCDATA _4 0 3 KBCDATA _3 0 2 KBCDATA _2 0 1 KBCDATA _1 0 0 KBCDATA _0 0
Symbol KBCDATA[7:0]
Function When the 8051 core reads from this register, the data returned is the last data byte written by the LPC Host to port 60H (if C/D bit is 0), or the last command byte written by the LPC Host to port 64H (if C/D bit is 1). The IBF bit in the status register is also cleared when the 8051 core reads this register. The 8051 core writes to this register the data byte from the KBC or keyboard, which will be returned to the LPC Host on the next read from port 60H. The OBF bit in the status register is set, and the internal KOBF signal is asserted when the 8051 core writes to this register. See Table 18-2.
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Advance Information 18.2.2 Keyboard Status Register (KBCSTS)
Location Read 7FF2H Write Reset 0 0 7 UD 6 UD 5 AUXOBF/ UD 0 4 UD 0 3 C/D 0 2 UD 0 1 IBF 0 0 OBF 0
Symbol UD AUXOBF/UD
IBF
OBF
Function Not implemented User defined bits. Can be written/read by the 8051 core. Auxiliary Output Buffer Full flag (if AUXSEL=1) or User defined bit (if AUXSEL=0) If AUXSEL=1 in KBDCFG register this read only bit is controlled by hardware as follows: Set to `1' when 8051 writes into the AUXDATA register at 7FFAH Cleared to `0' when 8051 writes into the KBCDATA register at 7FF1H C/D Command/Data flag (read only) Set to `1' when the LPC Host writes command byte to port 64H Cleared to `0' when the LPC Host writes data byte to port 60H Input Buffer Full flag (read only) Set when the LPC Host writes data or command to port 60H or 64H Cleared when the 8051 core reads KBCDATA register at address 7FF1H Interrupt request KCIBF to 8051 is asserted when this bit is set Output Buffer Full flag (read only) Set when the 8051 core writes into KBCDATA register at address 7FF1H or into AUXDATA register at address 7FFAH Cleared when the LPC Host reads port 60H Interrupt request KCOBE to 8051 is asserted when this bit is cleared
18.2.3 Keyboard Auxiliary Data Register (AUXDATA)
Location Read 7FFAH Write Reset 7 AUXDATA _7 0 6 AUXDATA _6 0 5 AUXDATA _5 0 4 AUXDATA _4 0 3 AUXDATA _3 0 2 AUXDATA _2 0 1 AUXDATA _1 0 0 AUXDATA _0 0
Symbol AUXDATA[7:0]
Function When the 8051 core reads from this register the data returned is the last 8051 written data. The 8051 core writes to this register the data byte from Mouse/Auxiliary Device which will be returned to the LPC Host on the next read from port 60H. The OBF bit in the status register is set, and the internal MOBF signal is asserted, when the 8051 core writes to this register. See Table 18-2.
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Advance Information 18.2.4 Keyboard Controller Configuration Register (KBDCFG)
Location Read 7FF4H Write Reset 0 X 0 7 AUXSEL 6 5 OBFEN 4 AUXOBFEN 0 3 X 2 PCOBFE N 0 1 SAEN 0 0 X
Symbol X AUXSEL
OBFEN
AUXOBFEN
PCOBFEN
SAEN
Function Not implemented Not defined Enable hardware control of Auxiliary Output buffer full status flag 1: AUXOBF bit in the status register is controlled by hardware write at address 7FFAH or 7FF1H 0: AUXOBF bit in the status register is a user defined bit (UD) controlled by 8051 software. KIRQ control bit 1: KIRQ follows PCOBF state 0: KIRQ is forced low (de-asserted) PCOBF is an internal signal, which reflects the status of 8051 and writes at address 7FF1H or at address 7FFDH. KIRQ is an internal source of IRQ1 interrupt for Serial IRQ transmission. See Figure 18-1 for KBC Interrupt Control diagram. MIRQ control bit 1: MIRQ follows MOBF state 0: MIRQ is forced low (de-asserted) MOBF is an internal signal, which reflects the status of 8051 and writes at address 7FFAH. MIRQ is an internal source of IRQ12 interrupt for Serial IRQ transmission. See Figure 18-1 for KBC Interrupt Control diagram. Select PCOBF source 1: PCOBF signal reflects the value of bit 0 in the PCOBF register at address 7DDFH (PCOBF = PCOBFL) 0: PCOBF reflects the status of 8051 and writes to KBCDATA register at address 7FF1H (PCOBF = KOBF) GA20 Software control Enable bit 1: Enable software control of GA20 pin 0: Enable hardware control of GA20 pin
18.2.5 PCOBF Register (PCOBF)
Location Read 7FFDH Write Reset X X X X X X X 0 7 6 5 4 3 2 1 0 PCOBFL
Symbol X PCOBFL
Function Not implemented Not defined PCOBF firmware controlled latch PCOBF signal reflects the value of this bit provided PCOBFEN=1. See Figure 18-1
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Advance Information 18.2.6 IRQ1 and IRQ12 Control After SST79LF008 chip reset, all the KBC status flags and the internal control signals PCOBF, KOBF, and MOBF are reset to 0. Respectively, KIRQ and MIRQ requests are deasserted low, which results in both IRQ1 and IRQ12 being reported to the LPC Host as "low" via Serialized IRQ bus. At run time the status flags and the internal control signals are changed in hardware according to Table 18-2.
TABLE 18-2: KBC Output Buffer Flags Control
Operation 8051 Writes to KBCDATA register at address 7FF1H 8051 Writes to AUXDATA register at address 7FFAH LPC Host reads Port 60H MOBF@7FFA No Change 1 0 KOBF@7FF1 1 No Change 0 OBF (KBCSTS[0]) 1 1 0 AUXOBF1 (KBCSTS[5]) 0 1 No Change
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1. This flag is controlled by hardware only if AUXSEL = 1
KIRQ and MIRQ interrupt requests reflect changing in the status flags according to Tables 18-3 and 18-4 and Figure 18-1. Whenever KIRQ/MIRQ is asserted, IRQ1/ TABLE 18-3: KBC Interrupt Control
OBFEN (KBDCFG[5]) 0 1 1
1. X = Not defined
IRQ12 interrupts are reported to the LPC Host as "high" via Serialized IRQ bus
PCOBFEN (KBDCFG[2]) X1 0 1
KIRQ KIRQ is inactive and driven low KIRQ = KOBF KIRQ = PCOBFL
T18-3.0 1245
TABLE 18-4: Mouse Interrupt Control
AUXOBFEN (KBDCFG[4]) 0 1 MIRQ MIRQ is inactive and driven low MIRQ = MOBF
T18-4.0 1245
KOBF PCOBFL PCOBFEN MOBF
0 PCOBF 1 OBFEN KIRQ
AUXOBFEN
MIRQ
1245 KBC_ InterruptCtrl.0
FIGURE
18-1: KBC Interrupt Control
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Advance Information
18.3 Keyboard Matrix Scan Control
The SST79LF008 provides 16 scan outputs KSO[15:0] and 8 scan inputs KSI[7:0] for standard notebook keyboard matrix scanning. These lines can be accessed by 8051 firmware via the KEYSCAN register described below. 18.3.1 Keyboard Scan-In / Scan-Out Register (KEYSCAN)
Location 7F04H Read Write Reset 7 KSI7 0 6 KSI6 KSOINV 0 5 KSI5 KSEN 1 4 KSI4 KSOLOW 0 3 KSI3 KSOC3 0 2 KSI2 KSOC2 0 1 KSI1 KSOC1 0 0 KSI0 KSOC0 0
Symbol KSI[7:0]
KSOINV KSEN KSOLOW KSOC[3:0] TABLE 18-5: KSO[15:0] Control
KSEN 1 0 0 0 0 KSOLOW X1 1 1 0 0
Function Not implemented When the KEYSCAN register is read, it returns the state of KSI[7:0] pins via these read-only bits. Any KSI pin transitions from high to low will assert KEY interrupt request to 8051. Scanner output polarity control bit (write-only) Scanner enable mask (write-only) Scanner low output control bit (write-only) Scanner output selection bits (write-only)
KSOINV X 1 0 1 0
KSOC[3:0] X X X n n
KSO[15:0] All lines are high All lines are high All lines are low KSO[n] line is high and all other lines are low KSO[n] line is low, and all other lines are high (n = 15-0)
T18-5.0 1245
1. X = Not defined
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Advance Information
19.0 GA20 AND CPU RESET HARDWARE CONTROL
The keyboard controller GA20 output is a PC legacy feature, which provides capability to mask the address line A20 in order to emulate 8086 20-bit address space. Similarly the KBC to CPU reset output, KBRST#, is a legacy host CPU reset signal which can be triggered via the KBC. The SST79LF008 device contains on-chip logic to provide the host processor with direct control of GA20 and KBRST# outputs. This control is implemented via specific command/data sequences sent over LPC interface to ports 64H and 60H. Optionally, this on-chip logic can be disabled via SAEN bit in the KBDCFG register and SKBEN bit in the GA20 register, requesting control of the GA20 and/or KBRST# outputs to the 8051 firmware. TABLE 19-1: GA20 Command Sequences
I/O Port 64H 60H 64H 60H 64H 60H 64H 64H 60H 64H 64H 64H 64H R/W W W W W W W W W W W W W W VALUE D1 DF D1 DD D1 DF FF D1 DD FF D1 XX2 FF IBF 0 0 0 0 0 0 0 0 0 0 0 1 1 GA20 Q1 1 Q 0 Q1 1 1 Q 0 0 Q Q 0 Functions Set GA20 command Clear GA20 command Extended Set GA20 command Extended Clear GA20 command Invalid Sequence
19.1 GA20 State Machine
Table 19-1 lists typical GA20 command sequences sent by the LPC Host to control the GA20 output from KBC. The hardware GA20 state machine, which interprets these sequences when GA20 hardware is enabled, is shown in Figure 19-1. After SST79LF008 chip reset, the state machine is in S0 state. Note that during a valid GA20 command sequence the IBF flag in the KBC status register is not `1'. This makes the hardware GA20 control (when SAEN = 0) transparent to 8051 firmware.
T19-1.1320
1. Q means no changes 2. XX means any command code except D1
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Advance Information
RESET
S0
CMD != D1 or DATA [IBF=1]
CMD !=D1 [IBF=1]
CMD=D1 [IBF=0]
CMD=FF [IBF=0]
CMD!=D1 or CMD!=FF or DATA[IBF=1] CMD=D1 [IBF=0]
S1
CMD=D1 [IBF=0]
DATA[IBF=0] GA20=DATA[1]
S2
GA20 output updated on state transition from S1 to S2 CMD = byte written by the host to port 64H DATA = byte written by the host to port 60H
1245 GA20_StateMachine.0
FIGURE
19-1: GA20 State Machine
19.2 GA20 and KBRST# MMCRs
19.2.1 GA20 Output Register (GA20)
Location Read 7FFBH Write Reset X X X X 0 0 X 7 6 5 4 3 SKBEN 2 KBRST 1 0 GA20 GA20_SW 1
Symbol X SKBEN
KBRST
GA20 GA20_SW
Function Not implemented Not defined KBRST# Software control Enable bit 1: Enable KBRST# software control 0: Enable KBRST# hardware control KBRST# Pulse generation control bit Set/cleared by software. When SKBEN = 1, the `0' to `1' transition of this bit generates a pulse on KBRST# output (low going pulse with duration more than 6s). GA20 software control bit/Status flag Reading this bit returns the present state of the GA20 output signal Writing to this bit set/reset software controlled GA20_SW signal (which is output to GA20 pin provided SAEN = 1)
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Advance Information When SKBEN = 0, KBRST# hardware control is enabled, a KBRST# low going pulse is generated automatically in response to the LPC Host command FEH written to port 64H (pulse duration is 200 cycles of LPC clock LCLK). In this case the FEH command does not set the IBF flag in the KBC status register. When SKBEN = 1, 8051 firmware controls KBRST# pin, and it can generate KBRST# low going pulse by writing `0', and then `1' to the KBRST bit (pulse duration is 200 cycles of 8051 core clock CCLK). When SAEN'='0, GA20 hardware control is enabled, the GA20 output is controlled by the LPC Host command/data sequences written to ports 64H/60H as shown on Figure 19-1 and in Table 19-1. Additionally, in this mode, the 8051 core can set/reset GA20 line via SETGA20 and RSTGA20 registers described below. Since the LPC Host GA20 sequence and 8051 writes to SETGA20/RSTGA20 registers, they asynchronously control the same GA20 output. It is necessary for 8051 to read back the GA20 status via GA20 register to confirm the actual GA20 state.
19.2.2 Set GA20 Register (SETGA20)
Location Read 7FFEH Write Reset 0 0 0 0 0 0 0 0 7 SGA207 6 SGA206 5 SGA205 4 SGA204 3 SGA203 2 SGA20 1 SGA201 0 SGA200
Symbol SGA20[7:0]
Function Any writes to this register sets hardware controlled GA20 asynchronously. Read from this register always returns 00H.
19.2.3 Reset GA20 Register (RSTGA20)
Location Read 7FFFH Write Reset 0 0 0 0 0 0 0 0 7 RGA207 6 RGA206 5 RGA205 4 RGA204 3 RGA203 2 RGA20 1 RGA201 0 RGA200
Function Any writes to this register resets hardware controlled GA20 asynchronously. Read from this register always returns 00H. After SST79LF008 chip reset, the KBRST# signal is `1', When SAEN = 1, only the 8051 core controls GA20 pin via hardware controlled GA20_HW signal is `1', and software direct writes to bit 0 of GA20 register. The LPC Host comcontrolled GA20_SW signal is `0'. Reset value of mand detection is disabled when SAEN = 1, but writing to SAEN = 0, thus, GA20 status is returned by default as SETGA20 and RSTGA20 registers still affects the hardGA20_HW = 1. Note that both GA20 and KBRST# signals ware controlled GA20_HW signal, even though it is not outare multiplexed with GPIO pins, and should be properly put to GA20 pin. Note that hardware and software selected by 8051 firmware in order to utilize the respective controlled GA20 signals are independent. Figure 19-2 functions. shows how the LPC Host and KBC firmware controls the GA20 output.
8051 W to 7FFEH LPC Host Command via Port 60H/64H D En# Clear GPIOASEL[7] 8051 W to 7FFFH SAEN = KBDCFG[1] Set Q
Symbol RGA20[7:0]
GA20 GA20_SW GA20_HW 1 0 GA20 GPIO7 0 PIN GA20/GPIO7 1
1245 HostCtrlGA20.0
FIGURE
19-2: : Host and 8051 Control of GA20
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Advance Information
20.0 ACPI EMBEDDED CONTROLLER INTERFACE 20.1 ACPI Embedded Controller Interface Overview
ACPI specification defines a hardware and software interface between the operating system and an embedded controller (EC). This interface can be used by the standard operating system driver to directly communicate with the embedded controller. SST79LF008 provides two2 ACPI compliant EC interfaces ECI0 and ECI1. EC interface includes the following 8-bit registers: EC data write register, EC data read register, EC command write register, and EC status register. The host processor accesses EC interface registers at two addresses in the LPC I/O space. The 8051 core accesses EC interface registers at two addresses in the external data memory space. Figure 20-1 describes the register mapping to the host I/O space and 8051 memory space as well as access type for each register.
TABLE 20-1: Embedded Controller Interface Mapping
LPC Host I/O Address and Access Type Address1 62H for ECI0 68H for ECI1 Write 66H for ECI0 7F80H (ECIDATA1) for ECI1 6CH for ECI1 Read Host-from-EC status read Write/Read 7F54H (ECISTS) for ECI0 7F81H (ECISTS1) for ECI1
T20-1.1245
Function Host-to-EC data write Host-from-EC data read Host-to-EC command write
8051 Memory mapped Address and Access Type Access Read Write 7F80H (ECIDATA1) for ECI1 Read 7F53H (ECIDATA) for ECI0 Address (MMCR register) 7F53H (ECIDATA) for ECI0
Access Write Read
1. The default base address for EC host interface ports can be changed via SST79LF008 configuration registers (see Section 23.0). For simplicity the description in Section 20.1 refers to default addresses.
When the Host writes command byte to EC through port 66H (6CH), the ECISTSn_C/D bit is set and the ECISTSn_IBF bit is set in the respective EC status register. When the Host writes data byte to EC through port 62H (68H), the ECISTSn_C/D bit is cleared and the ECISTSn_IBF bit is set in the respective EC status register. When the Host reads data from EC through port 62H (68H), the ECISTSn_OBF bit in the respective EC status register is cleared. See detailed bit description for EC status registers in Section 20.2.
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Advance Information
20.2 Embedded Controller Interface MMCRs
20.2.1 ECI Data Register (ECIDATA)
Location Read 7F53H Write Reset 7 ECIDATA _7 0 6 ECIDATA _6 0 5 ECIDATA _5 0 4 ECIDATA _4 0 3 ECIDATA _3 0 2 ECIDATA _2 0 1 ECIDATA _1 0 0 ECIDATA _0 0
Symbol ECIDATA[7:0]
Function When 8051 core reads from this register, data returned is the last data byte written by the LPC Host to port 62H (if ECISTSn_C/D bit in ECISTS register is 0), or the last command byte written by the LPC Host to port 66H (if ECISTSn_C/D bit is 1). The ECISTSn_IBF bit in ECISTS register is also cleared when 8051 core reads this register. When 8051 core writes to this register, it provides data to be returned to the LPC Host on the next read from port 62H. The ECISTSn_OBF bit in ECISTS register is also set when 8051 core writes to this register.
20.2.2 ECI Data Register 1 (ECIDATA1)
Location Read 7F80H Write Reset 7 6 5 4 3 2 1 0 ECIDATA1_ 0 0 ECIDATA1 ECIDATA1 ECIDATA1 ECIDATA1 ECIDATA1 ECIDATA1 ECIDATA1 _7 _6 _5 _4 _3 _2 _1 0 0 0 0 0 0 0
Symbol ECIDATA1[7:0]
Function When 8051 core reads from this register, data returned is the last data byte written by the LPC Host to port 68H (if ECISTSn_C/D bit in ECISTS1 register is 0), or the last command byte written by the LPC Host to port 6CH (if ECISTSn_C/D bit is 1). The ECISTSn_IBF bit in ECISTS1 register is also cleared when 8051 core reads this register. When 8051 core writes to this register, it provides data to be returned to the LPC Host on the next read from port 68H. The ECISTSn_OBF bit in ECISTS1 register is also set when 8051 core writes to this register.
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Advance Information 20.2.3 ECI Status Register (ECISTS)
Location Read 7F54H Write Reset 0 0 0 0 7 UD 6 ECISTS_ SMI_EVT 5 ECISTS_ SCI_EVT 4 ECISTS_ BURST 3 ECISTS_ C/D 0 2 UD 1 ECISTS_ IBF 0 0 ECISTS_ OBF 0
0
Symbol UD ECISTS_SMI_EVT
ECISTS_SCI_EVT
ECISTS_BURST
ECISTS_C/D
ECISTS_IBF
ECISTS_OBF
Function Not implemented User defined bits. Can be written/read by 8051 SMI Event flag 1: SMI event is pending 0: No outstanding SMI events The ECISTS_SMI_EVT bit is a software controlled flag. Typically it is set when the embedded controller has detected an internal event that is to be processed by the system management interrupt SMI handler. SCI Event flag 1: SCI event is pending 0: No outstanding SCI events The ECISTS_SCI_EVT bit is a software controlled flag. Typically it is set when the embedded controller has detected an internal event that is to be processed by the operating system driver that handles system control interrupt SCI. Burst Mode flag 1: EC is in Burst Mode for polled command processing 0: EC is in normal mode for interrupt-driven command processing The ECISTSn_BURST bit is a software only controlled flag. It indicates the embedded controller resources are dedicated to processing EC command/data stream. Burst Mode speeds up communication with the operating system driver as it eliminates the overhead of SCIs processing. Command/Data flag (read only) Set to `1' when the LPC Host writes command byte to port 66H Cleared to `0' when the LPC Host writes data byte to port 62H Input Buffer Full flag (read only) Set when the LPC Host writes data or command to port 62H or 66H Cleared when 8051 reads ECIDATA register at address 7F53H Interrupt request ECIBF to 8051 is asserted when this bit is set Output Buffer Full flag (read only) Set when 8051 writes into ECIDATA register at address 7F53H Cleared when the LPC Host reads port 62H Interrupt request ECOBE to 8051 is asserted when this bit is cleared
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Advance Information 20.2.4 ECI Status Register 1 (ECISTS1)
Location Read 7F81H Write Reset 0 0 0 0 7 UD 6 5 4 ECISTS1 _BURST 3 ECISTS1 _C/D 0 2 UD 1 ECISTS1 _IBF 0 0 ECISTS1 _OBF 0 ECISTS1_ ECISTS1_ SMI_EVT SCI_EVT
0
Symbol UD ECISTS1_SMI_EVT
ECISTS1_SCI_EVT
ECISTS1_BURST
ECISTS1_C/D
ECISTS1_IBF
ECISTS1_OBF
Function Not implemented User defined bits. Can be read/written by 8051. SMI Event flag 1: SMI event is pending 0: No outstanding SMI events The SMI_EVT bit is a software only controlled flag. Typically it is set when the embedded controller detects an internal event to be processed by the system management interrupt SMI handler. SCI Event flag 1: SCI event is pending 0: No outstanding SCI events The ECISTS_SCI_EVT bit is a software-only controlled flag. Typically it is set when the embedded controller has detected an internal event that is to be processed by the operating system driver that handles system control interrupt SCI. Burst Mode flag 1: EC is in Burst Mode for polled command processing 0: EC is in normal mode for interrupt-driven command processing. The ECISTSn_BURST bit is a software-only controlled flag. It indicates the embedded controller resources are dedicated to processing EC command/data stream. Burst Mode speeds up communication with the operating system driver as it eliminates the overhead of SCIs processing. Command/Data flag (read only) Set to `1' when the LPC Host writes command byte to port 6CH Cleared to `0' when the LPC Host writes data byte to port 68H Input Buffer Full flag (read only) Set when the LPC Host writes data or command to port 68H or 6CH Cleared when 8051 reads ECIDATA1 register at address 7F80H Interrupt request ECIBF1 to 8051 is asserted when this bit is set Output Buffer Full flag (read only) Set when 8051 writes into ECIDATA1 register at address 7F80H Cleared when the LPC Host reads port 68H Interrupt request ECOBE1 to 8051 is asserted when this bit is cleared.
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Advance Information
20.3 SMI and SCI Control
In addition to the standard ACPI EC registers described in the Section 20.2, the SST79LF008 provides ECI configuration registers, which control SMI and SCI hardware generation from EC interface. As shown on Figure 20-1, both SMI and SCI interrupts are generated as active low level sig20.3.1 ECI Configuration Register (ECICFG)
Location Read 7F51H Write Reset X X 7 6 5 ECICFG _SMIW 0 4 ECICFG _SMISEL 0 3 ECICFG _SCIW 0 2 ECICFG _SCISEL 0 1 ECICFG _SCIEN 0 0 ECICFG _SMIEN 0
nals. A single SMI pin is shared by both ECI interfaces and mailbox interface as detailed in Section 21.0, and two SCI pins (EC_SCI and EC1_SCI) are dedicated to EC interfaces (ECI0 and ECI1, respectively).
Symbol X ECICFG_SMIW
ECICFG_SMISEL
ECICFG_SCIW
ECICFG_SCISEL
ECICFG_SCIEN
ECICFG_SMIEN
Function Not implemented Not defined SMI generation control bit 1: Generate SMI from ECI0 0: Do not generate SMI from ECI0 SMI source selection bit 1: Select ECISTSn_OBF (ECISTS.0) as SMI source (ECISTSn_OBF = 1 will cause SMI if ECICFGn_SMIEN is set) 0: Select ECICFGn_SMIW (ECICFG.5) as SMI source (ECICFGn_SMIW = 1 will cause SMI if ECICFGn_SMIEN is set) SCI generation control bit 1: Generate SCI from ECI0 0: Do not generate SCI from ECI0 SCI source selection bit 1: Select ECISTSn_OBF (ECISTS.0) as SCI source (ECISTSn_OBF = 1 will cause SCI if ECICFGn_SCIEN is set) 0: Select ECICFGn_SCIW (ECICFG.3) as SCI source (ECICFGn_SCIW = 1 will cause SCI if ECICFGn_SCIEN is set) SCI generation enable bit 1: Enable SCI generation from ECI0 0: Disable SCI generation from ECI0 SMI generation enable bit 1: Enabled SMI generation from ECI0 0: Disable SMI generation from ECI0
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Advance Information 20.3.2 ECI Configuration Register 1(ECICFG1)
Location Read 7F52H Write Reset X X 7 6 5 ECICFG1 _SMIW 0 4 ECICFG1 _SMISEL 0 3 ECICFG1 _SCIW 0 2 ECICFG1 _SCISEL 0 1 ECICFG1 _SCIEN 0 0 ECICFG1_ SMIEN 0
Symbol X ECICFG1_MIW
ECICFG1_SMISEL
ECICFG1_SCIW
ECICFG1_SCISEL
ECICFG1_SCIEN
ECICFG1_SMIEN
Function Not implemented Not defined SMI generation control bit 1: Generate SMI from ECI1 0: Do not generate SMI from ECI1 SMI source selection bit 1: Select ECISTSn_OBF (ECISTS1.0) as SMI source (ECISTSn_OBF = 1 will cause SMI if ECICFGn_SMIEN is set) 0: Select ECICFGn_SMIW (ECICFG1.5) as SMI source (ECICFGn_SMIW = 1 will cause SMI if ECICFGn_SMIEN is set) SCI generation control bit 1: Generate SCI from ECI1 0: Do not generate SCI from ECI1 SCI source selection bit 1: Select ECISTSn_OBF (ECISTS1.0) as SCI source (ECISTSn_OBF = 1 will cause SCI if ECICFGn_SCIEN is set) 0: Select ECICFGn_SCIW (ECICFG1.3) as SCI source (ECICFGn_SCIW = 1 will cause SCI if ECICFGn_SCIEN is set) SCI generation enable bit 1: Enable SCI generation from ECI1 0: Disable SCI generation from ECI1 SMI generation enable bit 1: Enabled SMI generation from ECI1 0: Disable SMI generation from ECI1
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Advance Information
ECISTS_OBF ECICFG_SCIW
1 SCI (ACPI ECI 0) 0 ECICFG_SCIEN EC_SCI#
ECICFG_SCISEL
ECISTS1_OBF ECICFG1_SCIW
1 SCI (ACPI ECI 1) 0 ECICFG1_SCIEN EC1_SCI#
ECICFG1_SCISEL
ECISTS_OBF ECICFG_SWIW
1 SMI (ACPI ECI 0) 0 ECICFG_SMIEN
ECICFG_SMISEL
ECISTS1_OBF ECICFG1_SWIW
1 SMI (ACPI ECI 1) 0 ECICFG1_SMIEN EC_SMI#
ECICFG1_SMISEL
MSMI_SRC MSMI_MASK#
MBX_SMI
1245 SCI_SMI GenDia.0
FIGURE
20-1: SCI and SMI Generation Diagram
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Advance Information
21.0 MAILBOX INTERFACE AND DATA TRANSFER BLOCK
The SST79LF008 mailbox interface provides the LPC Host and 8051 with an additional mechanism for software controlled communications. The mailbox (MBX) interface includes 32 command/data transfer registers, and 3 control registers. Mailbox registers are accessed by the Host via a pair of Index/Data ports mapped into the LPC I/O space. The default LPC I/O address of the MBX Index port is 00H and of the MBX Data port is 01H. The default addresses can be changed by 8051 firmware during the SST79LF008 initial configuration as described in Section 23.0. In order to access a mailbox register, the Host must write the respective access index to the MBX Index port and then read/ write data from/to the MBX data port. The 8051 can access any mailbox transfer register directly at the assigned address in the 8051 external data memory space. Refer to Table 21-1 and Table 21-2 for mailbox registers Host access indexes and 8051 memory addresses.
21.1 Mailbox Command/Data Transfer Registers
TABLE 21-1: Mailbox Command/Data Transfer Registers Map
Mailbox name Mailbox register 0 Mailbox register 1 Mail box register 2 Mail box register 3 Mailbox register 4 Mailbox register 5 Mailbox register 6 Mailbox register 7 Mailbox register 8 Mailbox register 9 Mailbox register A Mailbox register B Mailbox register C Mailbox register D Mailbox register E Mailbox register F Mailbox register 10 Mailbox register 11 Mailbox register 12 Mailbox register 13 Mailbox register 14 Mailbox register 15 Mailbox register 16 Mailbox register 17 Mailbox register 18 Mailbox register 19 Mailbox register 1A Mailbox register 1B Mailbox register 1C Mailbox register 1D
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Host Acess Index 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH
8051 Address 7F08H 7F09H 7F0AH 7F0BH 7F0CH 7F0DH 7F0EH 7F0FH 7F10H 7F11H 7F12H 7F13H 7F14H 7F15H 7F16H 7F17H 7F70H 7F71H 7F72H 7F73H 7F74H 7F75H 7F76H 7F77H 7F78H 7F79H 7F7AH 7F7BH 7F7CH 7F7DH
Function Host-to-8051 Mailbox command register 8051-to-Host Mailbox command register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register Mailbox data transfer register
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Advance Information TABLE 21-1: Mailbox Command/Data Transfer Registers Map (Continued)
Mailbox name Mailbox register 1E Mailbox register 1F Host Acess Index AEH AFH 8051 Address 7F7EH 7F7FH Function Mailbox data transfer register Mailbox data transfer register
T21-1.1320
21.1.1 Mailbox register 0 (MBX0)
Location Read 7F08H Write Reset 0 0 0 0 0 0 0 0 7 MBX0_7 6 MBX0_6 5 MBX0_5 4 MBX0_4 3 MBX0_3 2 MBX0_2 1 MBX0_1 0 MBX0_0
Symbol MBX0[7:0]
Function Host-to-8051 Mailbox command register When the Host writes to this register, an 8051 interrupt request MBXINT is asserted. The interrupt request is cleared when the 8051 reads data from this register. When the 8051 writes to this register, the data is ignored and the register is reset to 00H.
21.1.2 Mailbox register 1 (MBX1)
Location Read 7F09H Write Reset 0 0 0 0 0 0 0 0 7 MBX1_7 6 MBX1_6 5 MBX1_5 4 MBX1_4 3 MBX1_3 2 MBX1_2 1 MBX1_1 0 MBX1_0
Function 8051-to-Host Mailbox command register When the 8051 writes to this register, a mailbox SMI source bit, MSMI_SRC is asserted. The SMI source is cleared when the Host reads data from this register. When the Host writes to this register, the data is ignored and the register is reset to 00H. The mailbox registers 0 and 1 can be used by the Host software and 8051 firmware to create mailbox command protocol(s), and to provide a hand-shaking mechanism for shared access to the other 30 mailbox data transfer registers. 21.1.3 Mailbox registers 2-1F (MBX2 - MBX1F)
Location (see Table 21-1) Read Write Reset 0 0 0 0 0 0 0 0 7 MBXn_7 6 MBXn_6 5 MBXn_5 4 MBXn_4 3 MBXn_3 2 MBXn_2 1 MBXn_1 0 MBXn_0
Symbol MBX1[7:0]
Symbol MBXn[7:0]
Function Mailbox data transfer register (n = 2-1F) General purpose data transfer registers. Can be read/written by both Host and 8051
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Advance Information
21.2 Mailbox Control Registers
Only the LPC Host can access the Mailbox control registers. These registers are not mapped into 8051 memory space, and therefore can only be identified by the Host access indexes. These control registers are shown in Table 21-2. TABLE 21-2: Mailbox Control Registers Map
Mailbox name Mailbox register 94 Mailbox register 96 Mailbox register 97 HOST ACCESS INDEX 94H 96H 97H FUNCTION Host control of 8051 clock and shared flash access MBX SMI source register MBX SMI mask register
T21-2.1245
21.2.1 Mailbox register 94 (MBX94)
Location Read (see Table 21-2) Write Reset 7 IDLE 0 6 HOSTFLASH 0 5 4 MAP 3 EXECUTION 0 2 1 0 STP_CLK
X
0
X
X
0
Symbol X IDLE
HOSTFLASH
MAP
EXECUTION
STP_CLK
Function Not implemented Not defined 8051 Idle mode status flag 1: 8051 is in Idle mode 0: 8051 is not in Idle mode Flash interface ownership flag 1: LPC Host owns flash interface 0: 8051 owns flash interface This bit is set when the shared flash interface is released to the host because either (a) 8051 is running from the scratch ROM and the HOST_ACCESS bit in the SFSC register is set, or (b) 8051 is in Idle mode and 8051 core clock is stopped by setting the STP_CLK bit in MBX94 (this register). KBC flash mapping control bit 1: KBC flash area is mapped to LPC space 0: KBC flash area is not mapped to LPC space (LPC read access to KBC area returns 00H) The KBC flash area is Block0-Block1 = 128 KByte, or Block0 = 64 KByte depending on the status of ACON[1] bit - see Section 6.5. Note that if the 8051 doesn't map KBC flash area to the LPC space, then this bit is ignored. If the 8051 maps the KBC flash to the LPC space, then this bit controls whether the KBC flash area is visible to the LPC Host or not. LPC program/erase operation acceptance indicator 1: Last LPC Host triggered program/erase operation is accepted 0: Last LPC Host triggered program/erase operation has been ignored Stop 8051 clock request bit Set by the LPC Host to stop 8051 clock in order to gain access to the shared flash interface (this bit should be set only after 8051 has been put into Idle mode) Cleared by the LPC Host to signal the release of shared flash interface
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Advance Information 21.2.2 Mailbox register 96 (MBX96)
Location (see Table 21-2) Read Write Reset X X X X 7 6 5 4 3 MSMI_SR C 0 2 1 0 -
X
X
X
Symbol X MSMI_SRC
Function Not implemented Not defined Mailbox SMI source bit Set when 8051 writes to 8051-to-Host Mailbox register 1 Cleared when the LPC Host reads Mailbox register 1
21.2.3 Mailbox register 97 (MBX97)
Location (see Table 21-2) Read Write Reset X X X X 7 6 5 4 3 MSMI_M SK 0 2 X 1 X 0 X
Symbol X MSMI_MSK
Function Not implemented Not defined Mailbox SMI mask 1: Mask Mailbox SMI 0: Enable Mailbox SMI This bit affects both possible mechanisms for Mailbox SMI reporting (SMI# pin and Serialized IRQ2).
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Advance Information
22.0 SERIALIZED INTERRUPTS
The SST79LF008 device provides serialized interrupt output, SERIRQ, which can be used to report interrupts from SST79LF008 to the LPC Host according to the Serialized IRQ Specification for PCI Systems, Revision 6.0.
22.1 Serialized IRQ Cycle Overview
An example of the Serialized IRQ cycle is shown on Figure 22-1. The cycle always begins with the Start frame and ends with the Stop frame. There are maximum 32 IRQ/ Data frames between the start and stop frame. Each of the data frames includes three phases: Sample phase, Recovery phase, and Turn-around phase. The SERIRQ is considered Idle between Stop and Start Frames. The SERIRQ is Active between Start and Stop Frames.
SL or H LPCCLK
START FRAME H R T
IRQ0 FRAME S R T
IRQ1 FRAME S R T
IRQ2 FRAME S R T
SERIRQ
START1
DRIVER
IRQ1 IRQ14 FRAME S R T
HOST CONTROLLER IRQ15 FRAME S R T
NONE
IRQ1 STOP FRAME I2 H R T
NONE NEXT CYCLE
IOCHCK#FRAME S R T
LPCCLK
SERIRQ
STOP3
START4
DRIVER
NONE
IRQ15 SL = Slave Control
NONE R = Recovery
HOST CONTROLLER T = Turn-around S = Sample
Legend: H = Host Control
1. Start Frame pulse can be 4-8 clocks wide. 2. There may be none, or one or more idles states (I) during the STOP frame. 3. Stop Frame is two clocks wide for Quiet mode, three clocks wide for continuous mode. 4. The next SERIRQ cycle's Start Frame pulse may or may not start immediately after the turn-around of the Stop frame.
1245 SerialIRQ cycle.0
FIGURE
22-1: Serialized IRQ cycle.
22.2 Serialized IRQ Start Frame
There are two modes of operation for the generation of SERIRQ Start Frame: Continuous and Quiet mode. In Continuous mode, the SST79LF008 does not generate a Start Frame. The device just monitors SERIRQ input and waits for the LPC Host to initiate the Start Frame by driving SERIRQ line low for four to eight clocks. In Quite mode, the SST79LF008 generates the Start Frame when it detects any transition of the internal IRQ/ Data signals associated with serialized IRQs, see Section
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22.3. The device will not generate the start frame if the SERIRQ is already Active, and the IRQ/Data transition can be reported in the current SERIRQ Cycle. In order to initiate the Start Frame, the SST79LF008 drives the SERIRQ line low for one clock, and then immediately tri-states the line. The Host controller takes over driving the SERIRQ low during the next clock and will continue driving it for a period of three to seven clocks. Thus a total Start Frame low pulse width is from four to eight clocks.
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Advance Information After SST79LF008 chip reset, as well as after LPC Interface reset, the SST79LF008 is in the Continuous mode, therefore only the LPC Host can initiate the first Start Frame. A SERIRQ mode transition can only occur during the Stop Frame as described in Section 22.4. previous sample phase. During the turn-around phase, the SST79LF008 tri-states the SERIRQ. The above rules of Data Frame control are followed by the SST79LF008 regardless of which device has initiated the Start Frame. The Sample phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks equal to the IRQ/Data Frame number times three, minus one. The only three internal IRQ/Data signals that are actually sampled by the SST79LF008 are: KIRQ (associated typically with IRQ1 frame via configuration registers described in Section 23.0), MIRQ (associated typically with IRQ12 frame via configuration registers described in Section 23.0), and Mailbox SMI (associated with IRQ2 frame if SMIEN_IRQ2 bit in configuration space is set). Table 22-1 shows the default SERIRQ sampling periods for these three internal IRQ/Data signals. For all other non-associated frames the SERIRQ line is left tri-stated by the SST79LF008.
22.3 Serialized IRQ Data Frame
After a Start Frame low going edge has been initiated, SST79LF008 waits for the rising edge of the start pulse in order to start counting IRQ/Data Frames. Each IRQ/Data Frame has three clocks: Sample phase, Recovery phase, and Turn-around phase. During the sample phase, the SST79LF008 drives the SERIRQ pin low provided the last sampled IRQ/Data value associated with the respective frame was low. If the last sampled IRQ/Data value was high, or no IRQ/Data signal is associated with the respective frame, the SERIRQ line is left tri-stated. During the recovery phase, the SST79LF008 drives the SERIRQ high, if and only if, it had driven the SERIRQ low during the TABLE 22-1: SST79LF008 SERIRQ Sampling Periods
IRQ/Data Frame number 2 3 13 Reported System IRQ IRQ1 IRQ2 IRQ12
SST79LF008 Signal Sampled KIRQ (Section 18.0) MSMI_SRC (Section 20.0) MIRQ (Section 18.0)
Number of clocks past Start 5 8 38
T22-1.1245
22.4 Serialized IRQ Stop Frame
After all IRQ/Data Frames are completed the SERIRQ cycle is terminated by a Stop Frame, which is indicated by the SERIRQ line being kept low for two or three clocks. Only the Host controller can initiate the Stop Frame. If the Stop Frame low time is two clocks, then the next SERIRQ cycle is in the Quiet mode, and the SST79LF008 may initiate a Start Frame. If the Stop Frame low time is three clocks, then the next SERIRQ cycle is in the Continuous mode, and only the Host may initiate a Start Frame. In any mode, the next Start Frame can be initiated once two or more clocks have occurred after the rising edge of the Stop Frame's pulse.
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Advance Information
23.0 SST79LF008 CONFIGURATION
The SST79LF008 configuration module provides 8051 firmware with a flexible mechanism to relocate I/O interfaces within the LPC Host I/O address space.
23.1 Access to Configuration Registers
The 8051 access to configuration space is controlled by the SELCFG bit in the LPC bus monitor register, LPCMON. Any configuration register is accessed via a pair of CFGINDEX and CFGDATA ports. The LPCMON, CFGINDEX PORT and CFGDATA PORT registers are mapped into the 8051 external data memory address space as shown in Registers 23.1.1-23.1.3. 23.1.1 LPC Bus Monitor Register (LPCMON)
Location Read 7F8AH Write Reset 0 7 SELCFG 6 LPCMODE 0 5 X 4 X 3 X 2 X 1 LRSTCOREENB 0 0 LPCPD -
Symbol X SELCGF
LPCMODE
LRSTCOREENB
LPCPD
Function Not implemented Not defined Configuration space access control bit 1: Reserved. Do not use this setting. 0: Enable 8051 access to configuration registers (must always be enabled). LPC Memory cycle control bit 1: SST79LF008 responds to LPC Memory cycles on LPC bus. Firmware Memory cycles are ignored. 0: SST79LF008 responds to Firmware Memory cycles on LPC bus. LPC Memory cycles are ignored. LPC Soft reset control bit 1: LPC commands "Force/Release LPC Soft Reset" are ignored. 0: LPC commands "Force/Release LPC Soft Reset" are accepted. This bit can be set by 8051 firmware, but it is cleared only by SST79LF008 chip reset. LPCPD signal status flag (read only) This bit is equal to the inverse of LPCPD# input pin (reset value is not specified as it is passed through pin state).
23.1.2 Configuration INDEX PORT Register (CFGINDEX)
Location Read 7F8CH Write Reset 7 6 5 4 3 2 1 0 CFGINDEX CFGINDEX CFGINDEX CFGINDEX CFGINDEX CFGINDEX CFGINDEX CFGINDEX _7 _6 _5 _4 _3 _2 _1 _0 0 0 0 0 0 0 0 0
Symbol CFGINDEX[7:0]
Function Configuration register index
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Advance Information 23.1.3 Configuration DATA PORT Register (CFGDATA)
Location Read 7F8DH Write Reset 7 CFGDATA _7 0 6 CFGDATA _6 0 5 CFGDATA _5 0 4 CFGDATA _4 0 3 CFGDATA _3 0 2 CFGDATA _2 0 1 CFGDATA _1 0 0 CFGDATA _0 0
Symbol CFGDATA[7:0]
Function Configuration register data Configuration Registers Map is shown in the Table 23-1. To access any Global Configuration register (index 00H-2FH) the 8051 firmware should do the following. 1. Write the index of the configuration register into the CFGINDEX PORT. 2. Write/read the Global Configuration register through the CFGDATA PORT. To access any Device Configuration register (index 30H and above) the 8051 firmware should do one of the following steps. a) 1. Write 07H (the index of the Logical Device Number register) to the CFGINDEX PORT. 2. Write the number of the targeted logical device to the CFGDATA PORT. b) 1. Write the address of the Device Configuration register to the CFGINDEX PORT. 2. Write/read the Device Configuration register through the CFGDATA PORT.
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Advance Information
23.2 Configuration Registers Description
TABLE 23-1: Configuration Registers Map1
Index 07H 20H 21H 22H 25H Access Type R/W R R R W Reset Value2 00H BFH F0H Revision Number 00H Configuration Register Name Logical Device Number3 Manufacturer ID (read only) Device ID (read only) Device Revision (read only) Chip Control register 0 Bits [7:1] are reserved Bit 0 = 1: Soft reset of Configuration registers4 Chip Control register 1 Bits [7:1] are reserved Bit 0 = SMIEN_IRQ2 1: Frame 3 of the SERIRQ cycle (IRQ2) is used to report Mailbox SMI. 0: SMI# pin is used to report Mailbox SMI 01H = Device is active 00H = Device is inactive. The address of the device is not decoded. LPC I/O read and write cycles to the device are ignored. No SERIRQ data frames is associated with keyboard and mouse interrupts. Keyboard Data port LPC I/O address = 0000:A[11:3]:000 Command/Status port address = Data port address + 4 Keyboard Interrupt selection (no effect if Device is inactive) Mouse Interrupt selection (not effect if Device is inactive) 01H = Device is active 00H = Device is inactive. The address of device is not decoded. LPC I/O read and write cycles to the device are ignored. ACPI ECI0 Data port LPC I/O address = 0000:A[11:3]:0:A1:0 Command/Status port address = Data port address + 4 01H = Device is active 00H = Device is inactive. The address of device is not decoded. LPC I/O read and write cycles to the device are ignored. Mailbox Index port LPC I/O address = 0000:A[11:1]:0 Mailbox Data port address = Index port address + 1 GLOBAL CONFIGURATION REGISTERS
26H
R/W
00H
LOGICAL DEVICE 0 CONFIGURATION REGISTERS (KEYBOARD CONTROLLER) 30H R/W 00H
60H5,61H 70H 72H 30H
R/W R/W R/W R/W
00H,60H 01H 0CH 00H
LOGICAL DEVICE 1 CONFIGURATION REGISTERS (ACPI ECI0)
60H5,61H
R/W
00H,62H
LOGICAL DEVICE 2 CONFIGURATION REGISTERS (Mailbox 32 Byte Data Block) 30H R/W 00H
60H5,61H
R/W
00H,00H
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Advance Information TABLE 23-1: Configuration Registers Map1 (Continued)
Index 30H Access Type R/W Reset Value2 00H Configuration Register Name 01H = Device is active. 00H = Device is inactive; the address of device is not decoded; LPC I/O read and write cycles to the device are ignored. ACPI ECI1 Data port LPC I/O address 0000:A[11:3]:0:A1:0 Command/Status port address = Data port address + 4
T23-1.1320
LOGICAL DEVICE 3 CONFIGURATION REGISTERS (ACPI ECI1)
60H5, 61H
R/W
00H, 68H
1. Register at indexes not listed in the map are reserved and must not be written to by software. 2. All configuration registers are returned to their reset values specified above after the following reset events: Power-On Reset, External reset, Watchdog timer reset, Brown-Out reset, aLPC Soft reset, LPC Soft reset, and Configuration Soft reset (see also Section 5.2). 3. A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device. All accesses to device specific configuration registers with index above 30H (including the activate command) operate only on the selected logical device. 4. The hardware automatically clears this bit after soft reset is completed; there is no need for software to clear this bit. This soft reset only affects configuration registers. 5. Register at index 60H contains high byte of LPC I/O address - bits A[15:8], and register at index 61H contains low byte of LPC I/O address- bits A[7:0].
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Advance Information
24.0 ELECTRICAL SPECIFICATION 24.1 Absolute Maximum Stress Ratings
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias-55C to +125C Storage Temperature65C to +150C Supply Voltage on VDD and AVDD Pins to Ground Potential-0.3V to 3.8V D.C. Voltage on Any Pin with IPCI, IOPCI and IODPCI buffer type1 to Ground Potential-0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin with IOPCI and IODPCI buffer type to Ground Potential-2.0V to VDD+2.0V Voltage on Any Pin with AIO4 buffer type to Ground Potential-0.3V to AVDD Voltage on Any Other Pin to Ground Potential-0.3V to 5.5V Package Power Dissipation Capability (Ta=25C)1.0W Surface Mount Solder Reflow Temperature 260C for 10 seconds Output Short Circuit Current250 mA
1. Refer to Table 2-1 for pin buffer type assignments. 2. Outputs shorted for no more than one second. No more than one output shorted at a time.
24.2 Operating Conditions
TABLE 24-1: Operating Range
Range Commercial Ambient Temp 0C to + 70C VDD 3.0-3.6V AVDD 3.15-3.45V1 FOSC 32.768KHz FECLK 4-16 MHz2 8-33 MHz3
T24-1.1245
1. If accuracy of analog operations is not relevant for the particular application, AVDD range can be expanded to 3.0 - 3.6V, which would allow direct connection to VDD for the entire operating range. 2. If external clock is used as PLL input clock. 3. If external clock is used directly as 8051 core clock.
TABLE 24-2: AC Condition of Test
Input Rise/Fall Time Output Load 3 ns CL = 30 pF See Figure 24-1 and Figure 24-2
T24-2.1245
TABLE 24-3: Recommended System Power-up Timing
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up (VDD = VDD Min) to LPC Host Read Operation Power-up (VDD = VDD Min) to LPC Host Write Operation
Minimum 10 10
Units ms ms
T24-3.1245
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 24-4: Pin Capacitance (TA = 25oC; fc = 1MHz; VDD = AVDD = 3.3V; other pins open)
Parameter CINc
1
Description Clock Input Capacitance Input Capacitance I/O Pin Capacitance Output Pin Capacitance
Test Condition VINC = 0V VIN = 0V VI/O = 0V VOUT = 0V
Maximum 12 pF 12 pF 12 pF 12 pF
T24-4.1245
CIN1 CI/O1 COUT1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 24-5: Reliability Characteristics
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T24-5.1245
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
24.3 DC Electrical Characteristics
TABLE 24-6: DC Characteristics (TA=0 to 70oC, AVDD = VDD = 3.0 to 3.6V, AVSS = VSS = 0V) (1 of 3)
Symbol VIL VIH IIL VOL VOH VIL VIH IIL VIL VIH IIL VIL VIH IIL VOL VOH IO5 I_PD I Type2 AIO4 Parameter Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Leakage Current Input Low Voltage Input High Voltage Input Leakage Current Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage Min 2.0 -10 2.4 2.0 -10 2.0 10 2.0 -10 2.4 66 Typ Max 0.8 10 0.4 0.8 10 0.8 110 0.8 10 0.4 Unit V V A V V V V A V V A V V A V V Test Conditions AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max IOL=4mA IOH=-4mA AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max IOL=5mA IOH=-5mA
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 24-6: DC Characteristics (TA=0 to 70oC, AVDD = VDD = 3.0 to 3.6V, AVSS = VSS = 0V) (2 of 3)
Symbol VIL VIH IIL VOL VIL VIH IIL VOL VIL VIH IIL VOL VIL VIH IIL VOL VOH VIL VIH IIL VOL VT VTVT+ IIL OD4 SIO4_PU IPCI IOPCI IODPCI IOD5 Type2 IOD4 Parameter Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Switching threshold Schmitt trigger, negativegoing threshold Schmitt trigger, positive-going threshold Input Leakage Current with pull-up disabled with pull-up enabled Output Low Voltage Output High Voltage SIO5 Switching threshold Schmitt trigger, negativegoing threshold Schmitt trigger, positive-going threshold Input Leakage Current Output Low Voltage Output High Voltage -10 2.4 0.8 2.0 10 0.4 -10 -110 2.4 0.8 2.0 Min 2.0 -10 2.0 -10 -0.5 0.5 VDD -10 -0.5 0.5 VDD -10 0.9VDD -0.5 0.5 VDD -10 1.4 Typ Max 0.8 10 0.4 0.8 10 0.4 0.3 VDD VDD+0.5 10 0.1VDD 0.3 VDD VDD+0.5 10 0.1VDD 0.3 VDD VDD+0.5 10 0.4 V V V A V V V V A -66 1.4 10 -10 0.4 V V V V V A V V AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max IOL=5mA IOH=-5mA AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max IOL=4mA IOH=-4mA V V A V V A A Unit V V A V V Test Conditions AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max IOL=4mA AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max IOL=5mA AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max Iout=1.5mA AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max Iout=1.5mA Iout=-0.5mA AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max IOL=4mA
VOL VOH VT VTVT+ IIL VOL VOH
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 24-6: DC Characteristics (TA=0 to 70oC, AVDD = VDD = 3.0 to 3.6V, AVSS = VSS = 0V) (3 of 3)
Symbol VT VTVT+ IIL VOL VT VT+ VTIIL VIL VIH VBOD IDD PWR OSC1 SI_PU Type2 SIOD15 Parameter Switching threshold Schmitt trigger, negativegoing threshold Schmitt trigger, positive-going threshold Input Leakage Current Output Low Voltage Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negativegoing threshold Input Leakage Current Input Low Voltage (OSC1) Input High Voltage(OSC1) Brown-out Detection Voltage VDD Supply Current in Active Mode without Flash program/erase operation Active Mode with Flash program/erase operation Idle Mode 35 mA 0.8 -110 VSS 0.8 x VDD 2.05 -66 2.5 -10 0.2 x VDD 2.85 -10 1.4 2.0 0.8 2.0 10 0.4 Min Typ 1.4 Max Unit V V V A V V V V A V V V VDD = VDD Max LCLK=VILT/ VIHT at f=33MHz ECLK=VILT/ VIHT at f=14.318 MHz PLL running at f=32.2155 MHz f=32.768 KHz All outputs and inputs with pull-ups or pulldowns are open. All other inputs = VDD. VDD = VDD Max PLL stopped. Oscillator disabled. All outputs and inputs with pull-ups or pull-downs are open. All other inputs = VDD. AVDD = AVDD Max ADC clock frequency = 2MHz No external load on DAC outputs
T24-6.1245
Test Conditions AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max IOL=15mA AVDD=VDD=VDD Min AVDD=VDD=VDD Max VIN = GND to VDD, VDD=VDD Max AVDD=VDD=VDD Min AVDD=VDD=VDD Max
45 25
mA mA
Power Down Mode
150
uA
IDDA
PWR
AVDD Supply Current Active Mode ADC operation Active Mode DAC operation Standby Mode (ADC and DAC are disabled) 18 30 4 25 70 mA mA uA
1. Connect crystal oscillator circuitry to oscillator input and output pins according to the schematic on Figure 5-3. 2. See I/O buffer types description in Table 2-2.
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Advance Information
24.4 AC Electrical Characteristics
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <3 ns. Note: VIT = VINPUT Test V0T = VOUTPUT Test VIHT = VINPUT HIGH Test VILT = VINPUT LOW Test
1245 ACInOut Waveforms.0
FIGURE
24-1: AC Input/Output Reference Waveforms
Note: The above reference points apply to all AC measurements specified in this section unless explicitly stated otherwise. For AC condition of test and operating range see Table 24-1 and Table 24-2.
TO TESTER
TO DUT CL
1245 TestLoad Ex.0
FIGURE
24-2: A Test Load Example
24.4.1 LPC Interface and Firmware Memory Timing TABLE 24-7: LPC Clock Timing Parameters
Symbol TCYC THIGH TLOW Parameter LCLK Cycle Time LCLK High Time LCLK Low Time LCLK Slew Rate (peakto-peak) LRESET# Slew Rate Min 30 11 11 1 50 4 Max Units ns ns ns V/ns mV/ns
T24-7.1245
Tcyc Thigh 0.6 VDD Tlow 0.5 VDD 0.4 VDD 0.3 VDD 0.2 VDD
1245 LCLK WaveForm.0
0.4 VDD p-to-p (minimum)
FIGURE
24-3: LCLK Wave Form
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 24-8: LPC Read/Write Cycle Timing Parameters
Symbol TCYC TSU TDH TVAL1 TBP TSE TBE TES TON TOFF Parameter Clock Cycle Time Data Set Up Time to Clock Rising Clock Rising to Data Hold Time Clock Rising to Data Valid Byte Programming Time Sector-Erase Time Block-Erase Time Erase Suspend Latency Time Clock Rising to Active (Float to Active Delay) Clock Rising to Inactive (Active to Float Delay) 2 28 Min 30 7 0 2 11 60 60 60 20 Max Units ns ns ns ns s ms ms s ns ns
T24-8.1245
1. Minimum and maximum time have different loads. See PCI spec.
TABLE 24-9: LPC AC Input/Output Specifications1
Symbol IOH(AC) Parameter Switching Current High Min -12 VDD -17.1(VDD-VOUT Equation C2 (Test Point) IOL(AC) Switching Current Low 16 VDD 26.7 VOUT Equation D2 (Test Point) ICL ICH SLEWR SLEWF3 Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate 26.7 VOUT -25+(VIN+1)/0.015 25+(VIN-VDD-1)/0.015 1 1 4 4 38 VDD mA mA mA V/ns V/ns -32 VDD mA mA mA Max Units mA mA Conditions 0 < VOUT 0.3 VDD 0.3 VDD < VOUT < 0.9 VDD 0.7 VDD < VOUT < VDD VOUT = 0.7 VDD VDD >VOUT 0.6 VDD 0.6 VDD > VOUT > 0.1 VDD 0.18 VDD > VOUT > 0 -3 < VIN -1 VOUT = 0.18 VDD
VDD+4 > VIN VDD+1 0.2 VDD-0.6 VDD load 0.6 VDD-0.2 VDD load
T24-9.1245
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. See PCI spec 3. PCI specification output load is used
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
VTH LCLK VTEST TVAL VTL
SERIRQ, LAD [3:0] (Valid Output Data)
SERIRQ, LAD [3:0] (Float Output Data) TON TOFF
1245 OutputTimeParam.0
FIGURE
24-4: LPC Output Timing Parameters
VTH LCLK TSU TDH SERIRQ, LFRAME#, LAD [3:0] (Valid Input Data) Inputs Valid VTEST VTL
VMAX
1245 LPC InputTimeParam.0
FIGURE
24-5: LPC Input Timing Parameters
TABLE 24-10: LPC Interface Measurement Condition Parameters
Symbol VTH
1
Value 0.6 VDD 0.2 VDD 0.4 VDD 0.4 VDD 1
Units V V V V V/ns
T24-10.1245
VTL1 VTEST VMAX1 Input Signal Edge Rate
1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive than this. VMAX specified the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameters.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 24-11: LPC Reset Timing Parameters1
Symbol TLRSTP TLRSTF TLRSTD2 Parameter LRESET# Pulse Width LRESET# Low to Output Float LRESET# High to LFRAME# or SERIRQ Low (1st LPC Host access delay after LPC Reset) LRESET# Low to LFRAME# Low if reset during Sector-/Block-Erase or Program 150 Min 100 48 Max Units ns ns ns
TLRSTE3
60
s
T24-11.1245
1. Guaranteed by design 2. LPC Reset NOT during Program or Erase operation 3. LPC Reset during Program or Erase operation
TLRSTP LRESET# TLRSTE TLRSTF LAD[3:0] TLRSTD
LFRAME# SERIRQ
1245 LPC ResetTimeDia.0
FIGURE
24-6: LPC Reset Timing Diagram
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 24.4.2 External Clocks and Reset Timing TABLE 24-12: External Clocks and Reset Timing Parameters1
SYMBOL FOSC = 1/TOSC TOSCSU 1/TECLK = FECLK = FCCLK 1/TECLK = FECLK = FPLLI TECLKH/TECLK TECLKF TECLKR FRCLK TPLLON TCCLK TWLOW (TWHIGH) TWLOW (TWHIGH) TXRSTP TXRSTD TPURSTD PARAMETER Crystal Oscillator Frequency Crystal Oscillator Start Up time External Clock Frequency if used as 8051 clock External Clock Frequency if used as PLL input External Clock Duty Cycle External Clock Fall Time External Clock Rise Time Ring Oscillator Frequency Time to switch 8051 core clock to PLL output 8051 Core Clock Period requirements External interrupt input pulse low (high) time External timer input pulse low (high) time External Reset# pulse width External Reset# to LPC Host access delay External Reset# High to 8051 code start delay Power-up to 1st LPC Host access delay Power-up to 8051 code start delay 1st 30 2 12 48 10 10 10 10 8 8 4 40 Min Typ 32.768 1 5 33 16 60 5 5 24 300 + 16128/ FPLLO2 125 Max Units KHz s MHz MHz % ns ns MHz s ns TCCLK TCCLK TCCLK ms ms ms ms
T24-12.1245
1. Guaranteed by design 2. FPLLO - PLL output clock frequency in MHz (see Section 5.3.2)
TECLK TECLKF TECLKR
ECLK TECLKH TECLKL
1245 Ext_Int CLK TimeDia.0
FIGURE
24-7: External Input Clock Timing Diagram
TWLOW External Interrupt or T0-T2 input
TWHIGH
1245 Ext_InterruptTimeDia.0
FIGURE
24-8: External Interrupt Timing Diagram
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
VDDMin VDD TPURSTD
RESET#
TXRSTP TXRSTD
8051 Code Re-start 8051 Code Re-start
LFRAME# SERIRQ
1245 PwrUp_ExtReset.0
FIGURE
24-9: Power Up and External Reset Timing Diagram
24.4.3 SMBus Interface Timing
tLOW
SMBCLK
tR
tHIGH
tF tSU;DAT tSU;STA tSU;ST0
tHD;STA
SMBDAT
tHD;DAT
tBUF
P
S
S
P
1245 SMBus_TimingDia.1
FIGURE 24-10: SMBus Timing Diagram TABLE 24-13: SMBus Interface Timing Parameters1
Symbol FSMB TBUF THD:STA Parameter SMBus Operating Frequency Bus Free Time Between Stop and Start Condition Hold time after (repeated) Start Condition. After this period, the first clock is generated Repeated Start Condition setup time Stop Condition Setup Time Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock/Data Fall Time Clock/Data Rise Time 4.7 4.0 Min Max 100 Units kHz s s
TSU:STA TSU:STO THD:DAT TSU:DAT TLOW THIGH TF T R2
1. Guaranteed by design 2. Depends on pull-up value
4.7 4.0 90 250 4.7 4.0 300 1000
s s ns ns s s ns ns
T24-13.1245
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 24-14: SMBus Interface Measurement Reference Points
Symbol VTH VTL Value VT+ Max + 0.25V VT- Min - 0.15V Units V V
T24-14.1245
24.4.4 PS/2 Interface Timing
T7 T1 T2 1 2 3 T3 T4 4 5 T5
PS2CRn_ WR_DATA
T10 6 7 8 T6 9 10 11
T11
PS2C WR_C PS2C WR_D
PSCLK PSDAT PS2CRn_PS2_EN PS2CRn_PS2_T/R
PS2CRn_ WR_CLK
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
P
S
T9 T8
PS2STSn_RDATA_RDY Read Status Reg
T12 T13
Interrupt
1245 PS2_Ch_Rece
FIGURE 24-11: PS/2 Hardware State Machine Receive Timing Diagram Note: Solid (dashed) line indicates that PS/2 interface signal is driven by SST79LF008 (PS/2 peripheral device).
T10 T1 T2 T6 1 T4 2 T7 3 T8 T9 4 5 T11 6 7 8 9 T14 10 11 T16
PS2CRn_ WR_CLK PS2CRn_ WR_DATA
PSCLK PSDAT PS2CRn_PS2_EN PS2CRn_PS2_T/R PS2STSn_XMIT_IDLE
PS2CRn_ WR_CLK PS2CRn_ WR_DATA
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
T5
P
S
T12
T3
T13
Write Transmit Reg Interrupt
T15
1245 PS2_Ch_Xmit
FIGURE 24-12: PS/2 Hardware State Machine Transmit Timing Diagram Note: Solid (dashed) line indicates that PS/2 interface signal is driven by SST79LF008 (PS/2 peripheral device).
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 24-15: PS/2 Receive Timing Parameters1
Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Parameter Time from PS/2 state machine enabled in receive mode (PS2CRn_PS2_EN = 1 and PS2CRn_PS2_T/R = 0) to SST79LF008 PSCLK and PSDAT outputs are in High-Z state PSCLK period Duration of PSCLK active (high) Duration of PSCLK inactive (low) Setup time from input PSDAT transition to falling edge of PSCLK (SST79LF008 uses falling edge of PSCLK to sample PSDAT) Hold time from falling edge of PSCLK to input PSDAT transition (SST79LF008 uses falling edge of PSCLK to sample PSDAT) Time from falling edge of the 1st clock (Start bit) to falling edge of the 11th clock (Stop bit) Time from falling edge of the 11th clock (Stop bit) to SST79LF008 sets PS2STSn_RDATA_RDY bit and drives PSCLK low to inhibit the next transfer Time from SST79LF008 Status Register read (trailing edge of the read signal) to PS2STSn_RDATA_RDY bit cleared Time from SST79LF008 Status Register read (trailing edge of the read signal) to SST79LF008 PSCLK output is in High-Z state Time from PS/2 state machine disabled (PS2CRn_PS2_EN = 0) to SST79LF008 PSCLK and PSDAT outputs are configured according to the PS2CRn_WR_CLK and PS2CRn_WR_DATA bits Time from PS2STSn_RDATA_RDY bit low-to-high transition to PS/2 Channel interrupt generated Time from SST79LF008 Status Register read (trailing edge of the read signal) to PS/2 interrupt cleared 30 6 30 30 0 600 22 600 0 150 15 Min 6 Max 15 3002 Units ns s s s ns ns ms ns ns ns ns
T12 T13
150 0
ns ns
T24-15.1320
1. Guaranteed by design 2. These maximum limits applied by SST79LF008 hardware provided the respective time-out detection is enabled
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 24-16: PS/2 Transmit Timing Parameters1
Symbol T1 Parameter Time from PS/2 state machine enabled in receive mode (PS2CRn_PS2_EN = 1 and PS2CRn_PS2_T/R = 0) to SST79LF008 PSCLK and PSDAT outputs are in High-Z state Time from PS/2 state machine switched into transmit mode (PS2CRn_PS2_T/R = 1) to PSCLK line driven low Time from SST79LF008 transmit register write (trailing edge of the write signal) to PS2STSn_XMIT_IDLE bit cleared Time from SST79LF008 transmit register write (trailing edge of the write signal) to PSDAT line driven low Time from SST79LF008 transmit register write (trailing edge of the write signal) to SST79LF008 PSCLK output is in High-Z state Time from request-to-send state (PSCLK = 1, PSDAT = 0) to the 1st clock falling edge (Start bit) generated by the peripheral device PSCLK period Duration of PSCLK active (high) Duration of PSCLK inactive (low) Time from falling edge of the1st clock (Start bit) to rising edge of the 11th clock (Line Control bit) Time from falling edge of PSCLK to SST79LF008 PSDATA output is in High-Z state to transmit `1', or driven low to transmit `0' (the peripheral device uses rising edge of PSCLK to sample PSDATA) Time from rising edge of the 11th clock (Line Control bit) to PS_T/R bit cleared Time from PS_T/R bit cleared to PS2STSn_XMIT_IDLE bit set Time from rising edge of the 10th clock (Stop bit) to SST79LF008 PSDATA output is in High-Z state Time from PS2STSn_XMIT_IDLE bit low-to-high transition to PS/2 Channel interrupt generated Interrupt is cleared by reading the Status Register same as in receive mode - not shown. Time from PS/2 state machine disabled (PS2CRn_PS2_EN = 0) to SST79LF008 PSCLK and PSDAT outputs are configured according to the PS2CRn_WR_CLK and PS2CRn_WR_DATA bits 60 30 30 22 450 30 T4+ 90 2 252 3002 Min 6 Max 15 Units ns
T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
60
300 T5 + 0 150 T4+ 450
ns ns ns ns s ms s s s ms ns
T12 T13 T14 T15
90 30 30 30
450 150 600 150
ns ns ns ns
T16
6
15
ns
T24-16.1245
1. Guaranteed by design 2. These maximum limits applied by SST79LF008 hardware provided the respective time-out detection is enabled
TABLE 24-17: PS/2 Interrupt Timing in bit-banging mode1,2
Symbol T1 T2 Parameter Time from falling edge of PSCLK to PS/2 Channel Interrupt generated Time from SST79LF008 Status Register read (trailing edge of the read signal) to PS/2 interrupt cleared Min 60 Max 450 0 Units ns ns
T24-17.1245
1. In bit-banging mode PS/2 receive and transmit protocols are controlled by the 8051 firmware 2. Guaranteed by design
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
PSCLOCK
Read Satus Register
T1 T1 T2 T2
Interrupt
1245 PS2_Interrupt Timing.1
FIGURE 24-13: PS/2 Interrupt Timing in bit-banging mode TABLE 24-18: PS/2 Interface Measurement Reference Points
Symbol VTH VTL Value VT+ Max VT- Min Units V V
T24-18.1245
24.4.5 UART Timing
TXLXL
UART CLOCK
TQVXH TXHQX
OUTPUT DATA WRITE TO SBUF INPUT DATA CLEAR RI
0
TXHDV VALID
1
2
TXHDX
3
4
5
6
7
SET TI
VALID
VALID
VALID
VALID
VALID
VALID
VALID SET RI
1245 UART_TimingDia.0
FIGURE 24-14: UART Timing Diagram (Shift Register Mode)
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information TABLE 24-19: UART Timing Parameters1
8051 core clock frequency Symbol TXLXL TQVXH TXHQX TXHDXr TXHDV 12MHz Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input data Hold After Clock Rising Edge Clock Rising Edge to input Data Valid Min 1.0 700 50 0 700 Max 32MHz Min 0.375 179 0 0 179 Max Min 12 TCCLK2 10 TCCLK
2-
Variable Max 133 Units us ns ns ns 10 TCCLK2 - 133 ns
T24-19.1245
2 TCCLK2- 117 0
1. Guaranteed by design 2. TCCLK - 8051core clock period (see Table 24-12)
24.4.6 SPI Timing TABLE 24-20: SPI Timing Parameters1
Symbol TSU TDH TV TSSS TSSH TSCK TSCKH TSCK Parameter Data In Setup time Data In Hold time Data Out Valid time SS setup time. SS hold time Serial Clock cycle in master (slave) mode Serial Clock low time Serial Clock high time 1 1 2 (4) 1 1 Min 1 1 1 Max Units TCCLK2 TCCLK2 TCCLK2 TCCLK2 TCCLK2 TCCLK2 TCCLK2 TCCLK2
T24-20.1245
1. Guaranteed by design 2. TCCLK - 8051core clock period (see Table 24-12)
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
TSCK TSCKH SCK CPOL=0 TSCKL
SCK CPOL=1
MOSI (to Slave) TV MISO (from Slave) TSU TDH
1245 SPImater_CPHA0.0
FIGURE 24-15: SPI Master Timing Diagram (CPHA=0, MSTR = 1)
TSCK TSCKH SCK CPOL=0 TSCKL
SCK CPOL=1
MOSI (to Slave) TV MISO (from Slave) TSU TDH
1245 SPImater_CPHA-1.0
FIGURE 24-16: SPI Master Timing Diagram (CPHA=1, MSTR = 1)
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
SS# Input (from Master)
TSSS TSCKH
TSCK TSCKL
TSSH
SCK CPOL=0
SCK CPOL=1
MISO (to Master) TV MOSI (from Master) TSU TDH
1245 SPIslave_CPHA-0.1
FIGURE 24-17: SPI Slave Timing Diagram (CPHA=0, MSTR = 0)
SS# Input (from Master)
TSSS TSCKH
TSCK TSCKL
TSSH
SCK CPOL=0
SCK CPOL=1
MISO (to Master) TV MOSI (from Master) TSU TDH
1245 SPIslave_CPHA-1.1
FIGURE 24-18: SPI Slave Timing Diagram (CPHA=1, MSTR = 0)
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information 24.4.7 PWM and FAN Tachometer Timing
PWM Prescaler Clock
PWM Output
Data Out TPWMV
1245 PWM OutputSignal.0
FIGURE 24-19: PWM Output Signals Timing Diagram TABLE 24-21: PWM Output Timing Parameters1
Symbol TPWMV Parameter PWM Output Valid Time Min 0 Max 0.5 Units TCCLK2
T24-21.1245
1. Guaranteed by design 2. TCCLK - 8051core clock period (see Table 24-12)
(c)2006 Silicon Storage Technology, Inc.
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10/06
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
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TFW TFH Fan Tachometer Input
1245 FanTachInput.0
TFL
FIGURE 24-20: FAN Tachometer Input Timing Diagram TABLE 24-22: FAN Tachometer Input Timing Parameters1
Symbol TFW TFH TFL Parameter Fan Tachometer Input Pulse Width Fan Tachometer Input Pulse High Time Fan Tachometer Input Pulse Low Time Min 4 3 1 Max Units TFTCLK2 TFTCLK2 TFTCLK2
T24-22.1245
1. Guaranteed by design 2. TFTCLK is a period of the clock used for the tachometer counter (see Section 5.2)
24.4.8 aLPC Interface Timing
TALCLK aLCLK TVALD THLD aLAD Output TVALF aLFRAME Output TSU aLAD Input
1245 aLPC-timing.0
TALCLKL
TALCLKH
TDH
FIGURE 24-21: aLPC Timing Diagram TABLE 24-23: aLPC Timing Parameters1
Symbol TALCLK TALCLK TALCLKH TACLKL THLD TVALD TVALF TSU TDH TARSTD Parameter aLCLK Clock Cycle Time before entry to the aLPC aLCLK Clock Cycle Time in the aLPC mode3 aLCLK Clock High Time aLCLK Clock Low Time Clock Rising to Output Data Hold Clock Rising to Output Data Valid Clock Falling to Output aLFARME Valid Input Data Set Up Time to Clock Falling Clock Falling to Input Data Hold Time aLPC mode entry to 1st aLPC Host access delay aLPC mode exit to 1st LPC Host access delay mode2 MIN 1250 200 80 80 0 2 5 10 5 15000 + 8*TALCLK 20 20 MAX UNITS ns ns ns ns ns ns ns ns ns ns
T24-23.1245
1. Guaranteed by design 2. During Enable_and_Poll and Switch_and_Reset sequences followed by reset completion delay TARSTD 3. After TARSTD delay
(c)2006 Silicon Storage Technology, Inc. S71320-01-000 10/06
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
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24.5 Analog Characteristics
24.5.1 ADC Characteristics TABLE 24-24: ADC Characteristics (TA=0 to 70C, VDD = 3.0-3.6V, AVDD = 3.15-3.45V, AVSS = VSS = 0V)
Symbol Bit AINT1 DNL INL TOPOFF BOTOFF1 FC Parameter Resolution Analog Input Voltage Differential Non-Linearity Error Integral Non-Linearity Error Offset Voltage Maximum Conversion Rate -8 0 0.8 1.0 3 Min Typ 10 AVDD 1 2 8 400 Max Units Bits V LSB LSB LSB KSPS ADC clock frequency = 2.0 MHz
T24-24.1245
Conditions
1. Guaranteed by design
24.5.2 DAC Characteristics TABLE 24-25: DAC Characteristics (TA=0 to 70C, VDD = 3.0-3.6V, AVDD = 3.15-3.45V, AVSS = VSS = 0V, RL >= 100k, CL <= 50pF)
Symbol Bit DNL INL VFS VZSE VFSE VOMAX2 VLSB2 Parameter Resolution Differential Non-Linearity Error Integral Non-Linearity Error Full Scale Voltage Zero Scale Error Full Scale Voltage Error Maximum Output Voltage LSB Size Channel Crosstalk2,3 3.187 12.11 3.087 Min Typ 8 0.3 0.5 3.207 40 40 3.247 12.58 -40 1.0 1.0 3.287 100 100 3.287 12.89 -30 Max Units Bits LSB LSB V mV mV V mV dB AVDD = 3.3V AVDD = 3.3V AVDD = 3.3V VFS = VOMAX - VOUT(00H)1 VZSE = VOUT(00H)1 VFSE = VOMAX - (AVDD*255/256) VOMAX = VOUT(FFH) VLSB = (VOMAX - VOUT(00H)1)/255 20*log(VPP max of unselected channel / VFS of selected channel) CL = 50pF RL = 100k CL = 50pF RL = 100k
T24-25.1245
Conditions
Comments
TS2,4 TON2,5 TONA2,6
Analog Output Settling Time Analog Output Enable Time
1 3 100
us us
1. VOUT(XXH) - actual DAC output voltage for input code XXH 2. Guaranteed by design 3. Peak-to-peak output voltage of unselected channel with input code 80H, when selected channel output voltage changes from VOUT(00H) to VOUT(FFH) 4. Time from loading data to output voltage settling within an error of +/- 0.5LSB 5. Time from the moment when DACENn = 1 in DACCTRL register to settling of the output voltage 6. Time from the moment when DACEN = 1 in DACCTRL register to settling of the output voltage
(c)2006 Silicon Storage Technology, Inc.
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10/06
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
25.0 PRODUCT ORDERING INFORMATION
SST 79 XX LF XX 008 - 33 XXX - XX C - BZ Y X - XX X E X Environmental Attribute F* = non-Pb (NiPdAu finish) E1 = non-Pb (pure Sn) Package Modifier R = 176 leads Y = 196 ball positions (196 possible) Package Type LR = LQFP (> 100 leads) BZ = TFBGA (> 100 ball sites) Operation Temperature C = Commercial: 0C to +70C Operating Frequency/Speed 33 = Maximum up to 33 MHz Flash Density 008 = 8 Mbit Function/Core F = Mobile Platform Controller LPC Firmware Flash Voltage L = 3.0 - 3.6V Product Series 79 = Application Specific Embedded Controller
* Environmental suffix "F" or "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant".
25.1 Valid Combinations
Valid combinations for SST79LF008 SST79LF008-33-C-LRRF SST79LF008-33-C-BZYE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2006 Silicon Storage Technology, Inc.
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Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
26.0 PACKAGING DIAGRAMS
TOP VIEW
20.00 BSC
0.23 0.13
22.00 BSC
0.40 BSC
Pin #1 Identifier
DETAIL
1.45 1.35
1.50 0.10
20.00 BSC
22.00 BSC
.20 .09
.15 .05
.75 .45
0- 7
1.00 nominal
1mm
NOTE: 1. Complies with JEDEC publication 95 MS-026 variant BFC dimensions although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.08 mm. 4. Package body dimensions do not include mold flash. Maximum allowable mold flash is 0.25 mm per side.
176-lqfp-LRR-1
FIGURE
26-1: 176-lead Low-profile Quad Flat Pack (LQFP) SST Package Code: LRR
(c)2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
251
Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008
Advance Information
TOP VIEW
12.00 0.10
BOTTOM VIEW
10.4 0.80
0.45 0.05 (176X)
14 13 12 11 10 9 8 7 6 5 4 3 2 1
ABCDEFGHJKLMNP A1 CORNER 1.20 maximum PNMLKJHGFEDCBA 0.80 12.00 0.10 10.4
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A1 CORNER
SIDE VIEW
0.12 0.35 0.05 Note:
1mm
SEATING PLANE
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 176-tfbga-BZY-12x12-450mic-2
FIGURE
26-2: 176-ball Thin-profile Fine-pitch Ball Grid Array (TFBGA) 12mm x 12mm SST Package Code: BZY
TABLE 26-1: Revision History
Number 00 01 Description Date May 2006 Oct 2006
* * * * * * * *
Initial Release of data sheet In Figure 2-1: Pin Assignments, modified pin description for pins B1 thru B7. In Figure 2-2: Pin Assignments, changed 052 to 152. In Table 4-4: IAP Commands, changed No Operation to No Reserve in row 1, and added a new row at bottom for No Operation. For Control Register "14.4.3.3 PS/2 Control Register 2 (PS2CR2)" on page 185, edited the PS2CRn_STOP[1:0] Function. In Table 24-6: DC Characteristics, revised VIL AND VIH Min. and Max vaules. Added paragraph (3rd) to "SPI Description" on page 159. Revised SPI Transfer Formats, Figure 12-2 and Figure 12-3
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2006 Silicon Storage Technology, Inc. S71320-01-000 10/06
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